forked from OSchip/llvm-project
925 lines
33 KiB
C++
925 lines
33 KiB
C++
//===- MachineCSE.cpp - Machine Common Subexpression Elimination Pass -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs global common subexpression elimination on machine
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// instructions using a scoped hash table based value numbering scheme. It
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// must be run while the machine function is still in SSA form.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/ScopedHashTable.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/CFG.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/MC/MCRegister.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/RecyclingAllocator.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <iterator>
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#include <utility>
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#include <vector>
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using namespace llvm;
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#define DEBUG_TYPE "machine-cse"
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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STATISTIC(NumCSEs, "Number of common subexpression eliminated");
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STATISTIC(NumPREs, "Number of partial redundant expression"
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" transformed to fully redundant");
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STATISTIC(NumPhysCSEs,
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"Number of physreg referencing common subexpr eliminated");
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STATISTIC(NumCrossBBCSEs,
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"Number of cross-MBB physreg referencing CS eliminated");
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STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
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namespace {
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class MachineCSE : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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AliasAnalysis *AA;
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MachineDominatorTree *DT;
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MachineRegisterInfo *MRI;
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MachineBlockFrequencyInfo *MBFI;
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public:
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static char ID; // Pass identification
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MachineCSE() : MachineFunctionPass(ID) {
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initializeMachineCSEPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<AAResultsWrapperPass>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineBlockFrequencyInfo>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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}
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties()
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.set(MachineFunctionProperties::Property::IsSSA);
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}
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void releaseMemory() override {
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ScopeMap.clear();
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PREMap.clear();
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Exps.clear();
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}
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private:
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using AllocatorTy = RecyclingAllocator<BumpPtrAllocator,
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ScopedHashTableVal<MachineInstr *, unsigned>>;
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using ScopedHTType =
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ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
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AllocatorTy>;
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using ScopeType = ScopedHTType::ScopeTy;
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using PhysDefVector = SmallVector<std::pair<unsigned, unsigned>, 2>;
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unsigned LookAheadLimit = 0;
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DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
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DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait>
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PREMap;
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ScopedHTType VNT;
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SmallVector<MachineInstr *, 64> Exps;
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unsigned CurrVN = 0;
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bool PerformTrivialCopyPropagation(MachineInstr *MI,
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MachineBasicBlock *MBB);
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bool isPhysDefTriviallyDead(MCRegister Reg,
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MachineBasicBlock::const_iterator I,
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MachineBasicBlock::const_iterator E) const;
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bool hasLivePhysRegDefUses(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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SmallSet<MCRegister, 8> &PhysRefs,
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PhysDefVector &PhysDefs, bool &PhysUseDef) const;
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bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<MCRegister, 8> &PhysRefs,
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PhysDefVector &PhysDefs, bool &NonLocal) const;
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bool isCSECandidate(MachineInstr *MI);
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bool isProfitableToCSE(Register CSReg, Register Reg,
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MachineBasicBlock *CSBB, MachineInstr *MI);
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void EnterScope(MachineBasicBlock *MBB);
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void ExitScope(MachineBasicBlock *MBB);
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bool ProcessBlockCSE(MachineBasicBlock *MBB);
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void ExitScopeIfDone(MachineDomTreeNode *Node,
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DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
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bool PerformCSE(MachineDomTreeNode *Node);
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bool isPRECandidate(MachineInstr *MI);
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bool ProcessBlockPRE(MachineDominatorTree *MDT, MachineBasicBlock *MBB);
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bool PerformSimplePRE(MachineDominatorTree *DT);
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/// Heuristics to see if it's profitable to move common computations of MBB
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/// and MBB1 to CandidateBB.
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bool isProfitableToHoistInto(MachineBasicBlock *CandidateBB,
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MachineBasicBlock *MBB,
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MachineBasicBlock *MBB1);
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};
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} // end anonymous namespace
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char MachineCSE::ID = 0;
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char &llvm::MachineCSEID = MachineCSE::ID;
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INITIALIZE_PASS_BEGIN(MachineCSE, DEBUG_TYPE,
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"Machine Common Subexpression Elimination", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(MachineCSE, DEBUG_TYPE,
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"Machine Common Subexpression Elimination", false, false)
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/// The source register of a COPY machine instruction can be propagated to all
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/// its users, and this propagation could increase the probability of finding
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/// common subexpressions. If the COPY has only one user, the COPY itself can
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/// be removed.
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bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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bool Changed = false;
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for (MachineOperand &MO : MI->operands()) {
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if (!MO.isReg() || !MO.isUse())
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continue;
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Register Reg = MO.getReg();
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if (!Register::isVirtualRegister(Reg))
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continue;
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bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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if (!DefMI->isCopy())
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continue;
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Register SrcReg = DefMI->getOperand(1).getReg();
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if (!Register::isVirtualRegister(SrcReg))
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continue;
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if (DefMI->getOperand(0).getSubReg())
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continue;
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// FIXME: We should trivially coalesce subregister copies to expose CSE
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// opportunities on instructions with truncated operands (see
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// cse-add-with-overflow.ll). This can be done here as follows:
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// if (SrcSubReg)
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// RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
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// SrcSubReg);
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// MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
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//
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// The 2-addr pass has been updated to handle coalesced subregs. However,
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// some machine-specific code still can't handle it.
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// To handle it properly we also need a way find a constrained subregister
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// class given a super-reg class and subreg index.
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if (DefMI->getOperand(1).getSubReg())
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continue;
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if (!MRI->constrainRegAttrs(SrcReg, Reg))
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continue;
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LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
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LLVM_DEBUG(dbgs() << "*** to: " << *MI);
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// Propagate SrcReg of copies to MI.
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MO.setReg(SrcReg);
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MRI->clearKillFlags(SrcReg);
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// Coalesce single use copies.
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if (OnlyOneUse) {
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// If (and only if) we've eliminated all uses of the copy, also
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// copy-propagate to any debug-users of MI, or they'll be left using
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// an undefined value.
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DefMI->changeDebugValuesDefReg(SrcReg);
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DefMI->eraseFromParent();
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++NumCoalesces;
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}
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Changed = true;
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}
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return Changed;
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}
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bool MachineCSE::isPhysDefTriviallyDead(
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MCRegister Reg, MachineBasicBlock::const_iterator I,
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MachineBasicBlock::const_iterator E) const {
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unsigned LookAheadLeft = LookAheadLimit;
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while (LookAheadLeft) {
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// Skip over dbg_value's.
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I = skipDebugInstructionsForward(I, E);
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if (I == E)
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// Reached end of block, we don't know if register is dead or not.
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return false;
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bool SeenDef = false;
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for (const MachineOperand &MO : I->operands()) {
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if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
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SeenDef = true;
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if (!MO.isReg() || !MO.getReg())
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continue;
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if (!TRI->regsOverlap(MO.getReg(), Reg))
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continue;
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if (MO.isUse())
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// Found a use!
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return false;
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SeenDef = true;
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}
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if (SeenDef)
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// See a def of Reg (or an alias) before encountering any use, it's
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// trivially dead.
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return true;
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--LookAheadLeft;
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++I;
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}
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return false;
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}
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static bool isCallerPreservedOrConstPhysReg(MCRegister Reg,
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const MachineFunction &MF,
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const TargetRegisterInfo &TRI) {
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// MachineRegisterInfo::isConstantPhysReg directly called by
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// MachineRegisterInfo::isCallerPreservedOrConstPhysReg expects the
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// reserved registers to be frozen. That doesn't cause a problem post-ISel as
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// most (if not all) targets freeze reserved registers right after ISel.
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//
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// It does cause issues mid-GlobalISel, however, hence the additional
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// reservedRegsFrozen check.
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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return TRI.isCallerPreservedPhysReg(Reg, MF) ||
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(MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
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}
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/// hasLivePhysRegDefUses - Return true if the specified instruction read/write
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/// physical registers (except for dead defs of physical registers). It also
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/// returns the physical register def by reference if it's the only one and the
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/// instruction does not uses a physical register.
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bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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SmallSet<MCRegister, 8> &PhysRefs,
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PhysDefVector &PhysDefs,
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bool &PhysUseDef) const {
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// First, add all uses to PhysRefs.
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg() || MO.isDef())
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continue;
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Register Reg = MO.getReg();
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if (!Reg)
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continue;
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if (Register::isVirtualRegister(Reg))
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continue;
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// Reading either caller preserved or constant physregs is ok.
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if (!isCallerPreservedOrConstPhysReg(Reg.asMCReg(), *MI->getMF(), *TRI))
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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PhysRefs.insert(*AI);
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}
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// Next, collect all defs into PhysDefs. If any is already in PhysRefs
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// (which currently contains only uses), set the PhysUseDef flag.
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PhysUseDef = false;
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MachineBasicBlock::const_iterator I = MI; I = std::next(I);
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for (const auto &MOP : llvm::enumerate(MI->operands())) {
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const MachineOperand &MO = MOP.value();
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if (!MO.isReg() || !MO.isDef())
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continue;
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Register Reg = MO.getReg();
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if (!Reg)
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continue;
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if (Register::isVirtualRegister(Reg))
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continue;
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// Check against PhysRefs even if the def is "dead".
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if (PhysRefs.count(Reg.asMCReg()))
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PhysUseDef = true;
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// If the def is dead, it's ok. But the def may not marked "dead". That's
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// common since this pass is run before livevariables. We can scan
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// forward a few instructions and check if it is obviously dead.
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if (!MO.isDead() && !isPhysDefTriviallyDead(Reg.asMCReg(), I, MBB->end()))
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PhysDefs.push_back(std::make_pair(MOP.index(), Reg));
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}
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// Finally, add all defs to PhysRefs as well.
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for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i)
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for (MCRegAliasIterator AI(PhysDefs[i].second, TRI, true); AI.isValid();
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++AI)
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PhysRefs.insert(*AI);
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return !PhysRefs.empty();
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}
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bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
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SmallSet<MCRegister, 8> &PhysRefs,
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PhysDefVector &PhysDefs,
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bool &NonLocal) const {
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// For now conservatively returns false if the common subexpression is
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// not in the same basic block as the given instruction. The only exception
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// is if the common subexpression is in the sole predecessor block.
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const MachineBasicBlock *MBB = MI->getParent();
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const MachineBasicBlock *CSMBB = CSMI->getParent();
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bool CrossMBB = false;
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if (CSMBB != MBB) {
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if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
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return false;
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for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
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if (MRI->isAllocatable(PhysDefs[i].second) ||
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MRI->isReserved(PhysDefs[i].second))
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// Avoid extending live range of physical registers if they are
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//allocatable or reserved.
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return false;
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}
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CrossMBB = true;
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}
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MachineBasicBlock::const_iterator I = CSMI; I = std::next(I);
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MachineBasicBlock::const_iterator E = MI;
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MachineBasicBlock::const_iterator EE = CSMBB->end();
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unsigned LookAheadLeft = LookAheadLimit;
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while (LookAheadLeft) {
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// Skip over dbg_value's.
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while (I != E && I != EE && I->isDebugInstr())
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++I;
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if (I == EE) {
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assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
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(void)CrossMBB;
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CrossMBB = false;
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NonLocal = true;
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I = MBB->begin();
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EE = MBB->end();
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continue;
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}
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if (I == E)
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return true;
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for (const MachineOperand &MO : I->operands()) {
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// RegMasks go on instructions like calls that clobber lots of physregs.
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// Don't attempt to CSE across such an instruction.
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if (MO.isRegMask())
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return false;
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if (!MO.isReg() || !MO.isDef())
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continue;
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Register MOReg = MO.getReg();
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if (Register::isVirtualRegister(MOReg))
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continue;
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if (PhysRefs.count(MOReg.asMCReg()))
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return false;
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}
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--LookAheadLeft;
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++I;
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}
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return false;
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}
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bool MachineCSE::isCSECandidate(MachineInstr *MI) {
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if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
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MI->isInlineAsm() || MI->isDebugInstr())
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return false;
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// Ignore copies.
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if (MI->isCopyLike())
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return false;
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// Ignore stuff that we obviously can't move.
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if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
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MI->mayRaiseFPException() || MI->hasUnmodeledSideEffects())
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return false;
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if (MI->mayLoad()) {
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// Okay, this instruction does a load. As a refinement, we allow the target
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// to decide whether the loaded value is actually a constant. If so, we can
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// actually use it as a load.
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if (!MI->isDereferenceableInvariantLoad(AA))
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// FIXME: we should be able to hoist loads with no other side effects if
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// there are no other instructions which can change memory in this loop.
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// This is a trivial form of alias analysis.
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return false;
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}
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// Ignore stack guard loads, otherwise the register that holds CSEed value may
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// be spilled and get loaded back with corrupted data.
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if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD)
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return false;
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return true;
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}
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/// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
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/// common expression that defines Reg. CSBB is basic block where CSReg is
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/// defined.
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bool MachineCSE::isProfitableToCSE(Register CSReg, Register Reg,
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MachineBasicBlock *CSBB, MachineInstr *MI) {
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// FIXME: Heuristics that works around the lack the live range splitting.
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// If CSReg is used at all uses of Reg, CSE should not increase register
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// pressure of CSReg.
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bool MayIncreasePressure = true;
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if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
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MayIncreasePressure = false;
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SmallPtrSet<MachineInstr*, 8> CSUses;
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for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
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CSUses.insert(&MI);
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}
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for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
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if (!CSUses.count(&MI)) {
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MayIncreasePressure = true;
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break;
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}
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}
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}
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if (!MayIncreasePressure) return true;
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// Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
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// an immediate predecessor. We don't want to increase register pressure and
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// end up causing other computation to be spilled.
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if (TII->isAsCheapAsAMove(*MI)) {
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MachineBasicBlock *BB = MI->getParent();
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if (CSBB != BB && !CSBB->isSuccessor(BB))
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return false;
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}
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// Heuristics #2: If the expression doesn't not use a vr and the only use
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// of the redundant computation are copies, do not cse.
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bool HasVRegUse = false;
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for (const MachineOperand &MO : MI->operands()) {
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if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
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HasVRegUse = true;
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break;
|
|
}
|
|
}
|
|
if (!HasVRegUse) {
|
|
bool HasNonCopyUse = false;
|
|
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
|
|
// Ignore copies.
|
|
if (!MI.isCopyLike()) {
|
|
HasNonCopyUse = true;
|
|
break;
|
|
}
|
|
}
|
|
if (!HasNonCopyUse)
|
|
return false;
|
|
}
|
|
|
|
// Heuristics #3: If the common subexpression is used by PHIs, do not reuse
|
|
// it unless the defined value is already used in the BB of the new use.
|
|
bool HasPHI = false;
|
|
for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
|
|
HasPHI |= UseMI.isPHI();
|
|
if (UseMI.getParent() == MI->getParent())
|
|
return true;
|
|
}
|
|
|
|
return !HasPHI;
|
|
}
|
|
|
|
void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
|
|
LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
|
|
ScopeType *Scope = new ScopeType(VNT);
|
|
ScopeMap[MBB] = Scope;
|
|
}
|
|
|
|
void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
|
|
LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
|
|
DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
|
|
assert(SI != ScopeMap.end());
|
|
delete SI->second;
|
|
ScopeMap.erase(SI);
|
|
}
|
|
|
|
bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
|
|
bool Changed = false;
|
|
|
|
SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
|
|
SmallVector<unsigned, 2> ImplicitDefsToUpdate;
|
|
SmallVector<unsigned, 2> ImplicitDefs;
|
|
for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
|
|
if (!isCSECandidate(&MI))
|
|
continue;
|
|
|
|
bool FoundCSE = VNT.count(&MI);
|
|
if (!FoundCSE) {
|
|
// Using trivial copy propagation to find more CSE opportunities.
|
|
if (PerformTrivialCopyPropagation(&MI, MBB)) {
|
|
Changed = true;
|
|
|
|
// After coalescing MI itself may become a copy.
|
|
if (MI.isCopyLike())
|
|
continue;
|
|
|
|
// Try again to see if CSE is possible.
|
|
FoundCSE = VNT.count(&MI);
|
|
}
|
|
}
|
|
|
|
// Commute commutable instructions.
|
|
bool Commuted = false;
|
|
if (!FoundCSE && MI.isCommutable()) {
|
|
if (MachineInstr *NewMI = TII->commuteInstruction(MI)) {
|
|
Commuted = true;
|
|
FoundCSE = VNT.count(NewMI);
|
|
if (NewMI != &MI) {
|
|
// New instruction. It doesn't need to be kept.
|
|
NewMI->eraseFromParent();
|
|
Changed = true;
|
|
} else if (!FoundCSE)
|
|
// MI was changed but it didn't help, commute it back!
|
|
(void)TII->commuteInstruction(MI);
|
|
}
|
|
}
|
|
|
|
// If the instruction defines physical registers and the values *may* be
|
|
// used, then it's not safe to replace it with a common subexpression.
|
|
// It's also not safe if the instruction uses physical registers.
|
|
bool CrossMBBPhysDef = false;
|
|
SmallSet<MCRegister, 8> PhysRefs;
|
|
PhysDefVector PhysDefs;
|
|
bool PhysUseDef = false;
|
|
if (FoundCSE &&
|
|
hasLivePhysRegDefUses(&MI, MBB, PhysRefs, PhysDefs, PhysUseDef)) {
|
|
FoundCSE = false;
|
|
|
|
// ... Unless the CS is local or is in the sole predecessor block
|
|
// and it also defines the physical register which is not clobbered
|
|
// in between and the physical register uses were not clobbered.
|
|
// This can never be the case if the instruction both uses and
|
|
// defines the same physical register, which was detected above.
|
|
if (!PhysUseDef) {
|
|
unsigned CSVN = VNT.lookup(&MI);
|
|
MachineInstr *CSMI = Exps[CSVN];
|
|
if (PhysRegDefsReach(CSMI, &MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
|
|
FoundCSE = true;
|
|
}
|
|
}
|
|
|
|
if (!FoundCSE) {
|
|
VNT.insert(&MI, CurrVN++);
|
|
Exps.push_back(&MI);
|
|
continue;
|
|
}
|
|
|
|
// Found a common subexpression, eliminate it.
|
|
unsigned CSVN = VNT.lookup(&MI);
|
|
MachineInstr *CSMI = Exps[CSVN];
|
|
LLVM_DEBUG(dbgs() << "Examining: " << MI);
|
|
LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
|
|
|
|
// Prevent CSE-ing non-local convergent instructions.
|
|
// LLVM's current definition of `isConvergent` does not necessarily prove
|
|
// that non-local CSE is illegal. The following check extends the definition
|
|
// of `isConvergent` to assume a convergent instruction is dependent not
|
|
// only on additional conditions, but also on fewer conditions. LLVM does
|
|
// not have a MachineInstr attribute which expresses this extended
|
|
// definition, so it's necessary to use `isConvergent` to prevent illegally
|
|
// CSE-ing the subset of `isConvergent` instructions which do fall into this
|
|
// extended definition.
|
|
if (MI.isConvergent() && MI.getParent() != CSMI->getParent()) {
|
|
LLVM_DEBUG(dbgs() << "*** Convergent MI and subexpression exist in "
|
|
"different BBs, avoid CSE!\n");
|
|
VNT.insert(&MI, CurrVN++);
|
|
Exps.push_back(&MI);
|
|
continue;
|
|
}
|
|
|
|
// Check if it's profitable to perform this CSE.
|
|
bool DoCSE = true;
|
|
unsigned NumDefs = MI.getNumDefs();
|
|
|
|
for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || !MO.isDef())
|
|
continue;
|
|
Register OldReg = MO.getReg();
|
|
Register NewReg = CSMI->getOperand(i).getReg();
|
|
|
|
// Go through implicit defs of CSMI and MI, if a def is not dead at MI,
|
|
// we should make sure it is not dead at CSMI.
|
|
if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
|
|
ImplicitDefsToUpdate.push_back(i);
|
|
|
|
// Keep track of implicit defs of CSMI and MI, to clear possibly
|
|
// made-redundant kill flags.
|
|
if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
|
|
ImplicitDefs.push_back(OldReg);
|
|
|
|
if (OldReg == NewReg) {
|
|
--NumDefs;
|
|
continue;
|
|
}
|
|
|
|
assert(Register::isVirtualRegister(OldReg) &&
|
|
Register::isVirtualRegister(NewReg) &&
|
|
"Do not CSE physical register defs!");
|
|
|
|
if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), &MI)) {
|
|
LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
|
|
DoCSE = false;
|
|
break;
|
|
}
|
|
|
|
// Don't perform CSE if the result of the new instruction cannot exist
|
|
// within the constraints (register class, bank, or low-level type) of
|
|
// the old instruction.
|
|
if (!MRI->constrainRegAttrs(NewReg, OldReg)) {
|
|
LLVM_DEBUG(
|
|
dbgs() << "*** Not the same register constraints, avoid CSE!\n");
|
|
DoCSE = false;
|
|
break;
|
|
}
|
|
|
|
CSEPairs.push_back(std::make_pair(OldReg, NewReg));
|
|
--NumDefs;
|
|
}
|
|
|
|
// Actually perform the elimination.
|
|
if (DoCSE) {
|
|
for (const std::pair<unsigned, unsigned> &CSEPair : CSEPairs) {
|
|
unsigned OldReg = CSEPair.first;
|
|
unsigned NewReg = CSEPair.second;
|
|
// OldReg may have been unused but is used now, clear the Dead flag
|
|
MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
|
|
assert(Def != nullptr && "CSEd register has no unique definition?");
|
|
Def->clearRegisterDeads(NewReg);
|
|
// Replace with NewReg and clear kill flags which may be wrong now.
|
|
MRI->replaceRegWith(OldReg, NewReg);
|
|
MRI->clearKillFlags(NewReg);
|
|
}
|
|
|
|
// Go through implicit defs of CSMI and MI, if a def is not dead at MI,
|
|
// we should make sure it is not dead at CSMI.
|
|
for (unsigned ImplicitDefToUpdate : ImplicitDefsToUpdate)
|
|
CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
|
|
for (const auto &PhysDef : PhysDefs)
|
|
if (!MI.getOperand(PhysDef.first).isDead())
|
|
CSMI->getOperand(PhysDef.first).setIsDead(false);
|
|
|
|
// Go through implicit defs of CSMI and MI, and clear the kill flags on
|
|
// their uses in all the instructions between CSMI and MI.
|
|
// We might have made some of the kill flags redundant, consider:
|
|
// subs ... implicit-def %nzcv <- CSMI
|
|
// csinc ... implicit killed %nzcv <- this kill flag isn't valid anymore
|
|
// subs ... implicit-def %nzcv <- MI, to be eliminated
|
|
// csinc ... implicit killed %nzcv
|
|
// Since we eliminated MI, and reused a register imp-def'd by CSMI
|
|
// (here %nzcv), that register, if it was killed before MI, should have
|
|
// that kill flag removed, because it's lifetime was extended.
|
|
if (CSMI->getParent() == MI.getParent()) {
|
|
for (MachineBasicBlock::iterator II = CSMI, IE = &MI; II != IE; ++II)
|
|
for (auto ImplicitDef : ImplicitDefs)
|
|
if (MachineOperand *MO = II->findRegisterUseOperand(
|
|
ImplicitDef, /*isKill=*/true, TRI))
|
|
MO->setIsKill(false);
|
|
} else {
|
|
// If the instructions aren't in the same BB, bail out and clear the
|
|
// kill flag on all uses of the imp-def'd register.
|
|
for (auto ImplicitDef : ImplicitDefs)
|
|
MRI->clearKillFlags(ImplicitDef);
|
|
}
|
|
|
|
if (CrossMBBPhysDef) {
|
|
// Add physical register defs now coming in from a predecessor to MBB
|
|
// livein list.
|
|
while (!PhysDefs.empty()) {
|
|
auto LiveIn = PhysDefs.pop_back_val();
|
|
if (!MBB->isLiveIn(LiveIn.second))
|
|
MBB->addLiveIn(LiveIn.second);
|
|
}
|
|
++NumCrossBBCSEs;
|
|
}
|
|
|
|
MI.eraseFromParent();
|
|
++NumCSEs;
|
|
if (!PhysRefs.empty())
|
|
++NumPhysCSEs;
|
|
if (Commuted)
|
|
++NumCommutes;
|
|
Changed = true;
|
|
} else {
|
|
VNT.insert(&MI, CurrVN++);
|
|
Exps.push_back(&MI);
|
|
}
|
|
CSEPairs.clear();
|
|
ImplicitDefsToUpdate.clear();
|
|
ImplicitDefs.clear();
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
/// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
|
|
/// dominator tree node if its a leaf or all of its children are done. Walk
|
|
/// up the dominator tree to destroy ancestors which are now done.
|
|
void
|
|
MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
|
|
DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren) {
|
|
if (OpenChildren[Node])
|
|
return;
|
|
|
|
// Pop scope.
|
|
ExitScope(Node->getBlock());
|
|
|
|
// Now traverse upwards to pop ancestors whose offsprings are all done.
|
|
while (MachineDomTreeNode *Parent = Node->getIDom()) {
|
|
unsigned Left = --OpenChildren[Parent];
|
|
if (Left != 0)
|
|
break;
|
|
ExitScope(Parent->getBlock());
|
|
Node = Parent;
|
|
}
|
|
}
|
|
|
|
bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
|
|
SmallVector<MachineDomTreeNode*, 32> Scopes;
|
|
SmallVector<MachineDomTreeNode*, 8> WorkList;
|
|
DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
|
|
|
|
CurrVN = 0;
|
|
|
|
// Perform a DFS walk to determine the order of visit.
|
|
WorkList.push_back(Node);
|
|
do {
|
|
Node = WorkList.pop_back_val();
|
|
Scopes.push_back(Node);
|
|
OpenChildren[Node] = Node->getNumChildren();
|
|
append_range(WorkList, Node->children());
|
|
} while (!WorkList.empty());
|
|
|
|
// Now perform CSE.
|
|
bool Changed = false;
|
|
for (MachineDomTreeNode *Node : Scopes) {
|
|
MachineBasicBlock *MBB = Node->getBlock();
|
|
EnterScope(MBB);
|
|
Changed |= ProcessBlockCSE(MBB);
|
|
// If it's a leaf node, it's done. Traverse upwards to pop ancestors.
|
|
ExitScopeIfDone(Node, OpenChildren);
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
// We use stronger checks for PRE candidate rather than for CSE ones to embrace
|
|
// checks inside ProcessBlockCSE(), not only inside isCSECandidate(). This helps
|
|
// to exclude instrs created by PRE that won't be CSEed later.
|
|
bool MachineCSE::isPRECandidate(MachineInstr *MI) {
|
|
if (!isCSECandidate(MI) ||
|
|
MI->isNotDuplicable() ||
|
|
MI->mayLoad() ||
|
|
MI->isAsCheapAsAMove() ||
|
|
MI->getNumDefs() != 1 ||
|
|
MI->getNumExplicitDefs() != 1)
|
|
return false;
|
|
|
|
for (const auto &def : MI->defs())
|
|
if (!Register::isVirtualRegister(def.getReg()))
|
|
return false;
|
|
|
|
for (const auto &use : MI->uses())
|
|
if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
bool MachineCSE::ProcessBlockPRE(MachineDominatorTree *DT,
|
|
MachineBasicBlock *MBB) {
|
|
bool Changed = false;
|
|
for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
|
|
if (!isPRECandidate(&MI))
|
|
continue;
|
|
|
|
if (!PREMap.count(&MI)) {
|
|
PREMap[&MI] = MBB;
|
|
continue;
|
|
}
|
|
|
|
auto MBB1 = PREMap[&MI];
|
|
assert(
|
|
!DT->properlyDominates(MBB, MBB1) &&
|
|
"MBB cannot properly dominate MBB1 while DFS through dominators tree!");
|
|
auto CMBB = DT->findNearestCommonDominator(MBB, MBB1);
|
|
if (!CMBB->isLegalToHoistInto())
|
|
continue;
|
|
|
|
if (!isProfitableToHoistInto(CMBB, MBB, MBB1))
|
|
continue;
|
|
|
|
// Two instrs are partial redundant if their basic blocks are reachable
|
|
// from one to another but one doesn't dominate another.
|
|
if (CMBB != MBB1) {
|
|
auto BB = MBB->getBasicBlock(), BB1 = MBB1->getBasicBlock();
|
|
if (BB != nullptr && BB1 != nullptr &&
|
|
(isPotentiallyReachable(BB1, BB) ||
|
|
isPotentiallyReachable(BB, BB1))) {
|
|
// The following check extends the definition of `isConvergent` to
|
|
// assume a convergent instruction is dependent not only on additional
|
|
// conditions, but also on fewer conditions. LLVM does not have a
|
|
// MachineInstr attribute which expresses this extended definition, so
|
|
// it's necessary to use `isConvergent` to prevent illegally PRE-ing the
|
|
// subset of `isConvergent` instructions which do fall into this
|
|
// extended definition.
|
|
if (MI.isConvergent() && CMBB != MBB)
|
|
continue;
|
|
|
|
assert(MI.getOperand(0).isDef() &&
|
|
"First operand of instr with one explicit def must be this def");
|
|
Register VReg = MI.getOperand(0).getReg();
|
|
Register NewReg = MRI->cloneVirtualRegister(VReg);
|
|
if (!isProfitableToCSE(NewReg, VReg, CMBB, &MI))
|
|
continue;
|
|
MachineInstr &NewMI =
|
|
TII->duplicate(*CMBB, CMBB->getFirstTerminator(), MI);
|
|
|
|
// When hoisting, make sure we don't carry the debug location of
|
|
// the original instruction, as that's not correct and can cause
|
|
// unexpected jumps when debugging optimized code.
|
|
auto EmptyDL = DebugLoc();
|
|
NewMI.setDebugLoc(EmptyDL);
|
|
|
|
NewMI.getOperand(0).setReg(NewReg);
|
|
|
|
PREMap[&MI] = CMBB;
|
|
++NumPREs;
|
|
Changed = true;
|
|
}
|
|
}
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
// This simple PRE (partial redundancy elimination) pass doesn't actually
|
|
// eliminate partial redundancy but transforms it to full redundancy,
|
|
// anticipating that the next CSE step will eliminate this created redundancy.
|
|
// If CSE doesn't eliminate this, than created instruction will remain dead
|
|
// and eliminated later by Remove Dead Machine Instructions pass.
|
|
bool MachineCSE::PerformSimplePRE(MachineDominatorTree *DT) {
|
|
SmallVector<MachineDomTreeNode *, 32> BBs;
|
|
|
|
PREMap.clear();
|
|
bool Changed = false;
|
|
BBs.push_back(DT->getRootNode());
|
|
do {
|
|
auto Node = BBs.pop_back_val();
|
|
append_range(BBs, Node->children());
|
|
|
|
MachineBasicBlock *MBB = Node->getBlock();
|
|
Changed |= ProcessBlockPRE(DT, MBB);
|
|
|
|
} while (!BBs.empty());
|
|
|
|
return Changed;
|
|
}
|
|
|
|
bool MachineCSE::isProfitableToHoistInto(MachineBasicBlock *CandidateBB,
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock *MBB1) {
|
|
if (CandidateBB->getParent()->getFunction().hasMinSize())
|
|
return true;
|
|
assert(DT->dominates(CandidateBB, MBB) && "CandidateBB should dominate MBB");
|
|
assert(DT->dominates(CandidateBB, MBB1) &&
|
|
"CandidateBB should dominate MBB1");
|
|
return MBFI->getBlockFreq(CandidateBB) <=
|
|
MBFI->getBlockFreq(MBB) + MBFI->getBlockFreq(MBB1);
|
|
}
|
|
|
|
bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipFunction(MF.getFunction()))
|
|
return false;
|
|
|
|
TII = MF.getSubtarget().getInstrInfo();
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
MRI = &MF.getRegInfo();
|
|
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
|
DT = &getAnalysis<MachineDominatorTree>();
|
|
MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
|
|
LookAheadLimit = TII->getMachineCSELookAheadLimit();
|
|
bool ChangedPRE, ChangedCSE;
|
|
ChangedPRE = PerformSimplePRE(DT);
|
|
ChangedCSE = PerformCSE(DT->getRootNode());
|
|
return ChangedPRE || ChangedCSE;
|
|
}
|