forked from OSchip/llvm-project
317 lines
10 KiB
C++
317 lines
10 KiB
C++
//===-- AMDGPUTargetTransformInfo.cpp - AMDGPU specific TTI pass ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// \file
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// This file implements a TargetTransformInfo analysis pass specific to the
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// AMDGPU target machine. It uses the target's detailed information to provide
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// more precise answers to certain TTI queries, while letting the target
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// independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetTransformInfo.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "AMDGPUtti"
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void AMDGPUTTIImpl::getUnrollingPreferences(Loop *L,
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TTI::UnrollingPreferences &UP) {
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UP.Threshold = 300; // Twice the default.
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UP.MaxCount = UINT_MAX;
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UP.Partial = true;
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// TODO: Do we want runtime unrolling?
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for (const BasicBlock *BB : L->getBlocks()) {
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const DataLayout &DL = BB->getModule()->getDataLayout();
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for (const Instruction &I : *BB) {
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const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(&I);
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if (!GEP || GEP->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
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continue;
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const Value *Ptr = GEP->getPointerOperand();
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const AllocaInst *Alloca =
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dyn_cast<AllocaInst>(GetUnderlyingObject(Ptr, DL));
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if (Alloca) {
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// We want to do whatever we can to limit the number of alloca
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// instructions that make it through to the code generator. allocas
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// require us to use indirect addressing, which is slow and prone to
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// compiler bugs. If this loop does an address calculation on an
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// alloca ptr, then we want to use a higher than normal loop unroll
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// threshold. This will give SROA a better chance to eliminate these
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// allocas.
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//
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// Don't use the maximum allowed value here as it will make some
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// programs way too big.
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UP.Threshold = 800;
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}
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}
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}
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}
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unsigned AMDGPUTTIImpl::getNumberOfRegisters(bool Vec) {
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if (Vec)
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return 0;
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// Number of VGPRs on SI.
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if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
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return 256;
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return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
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}
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unsigned AMDGPUTTIImpl::getRegisterBitWidth(bool Vector) {
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return Vector ? 0 : 32;
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}
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unsigned AMDGPUTTIImpl::getMaxInterleaveFactor(unsigned VF) {
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// Semi-arbitrary large amount.
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return 64;
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}
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int AMDGPUTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo) {
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EVT OrigTy = TLI->getValueType(DL, Ty);
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if (!OrigTy.isSimple()) {
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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// Legalize the type.
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std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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// Because we don't have any legal vector operations, but the legal types, we
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// need to account for split vectors.
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unsigned NElts = LT.second.isVector() ?
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LT.second.getVectorNumElements() : 1;
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MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy;
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switch (ISD) {
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA: {
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if (SLT == MVT::i64)
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return get64BitInstrCost() * LT.first * NElts;
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// i32
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return getFullRateInstrCost() * LT.first * NElts;
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}
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case ISD::ADD:
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case ISD::SUB:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR: {
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if (SLT == MVT::i64){
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// and, or and xor are typically split into 2 VALU instructions.
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return 2 * getFullRateInstrCost() * LT.first * NElts;
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}
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return LT.first * NElts * getFullRateInstrCost();
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}
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case ISD::MUL: {
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const int QuarterRateCost = getQuarterRateInstrCost();
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if (SLT == MVT::i64) {
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const int FullRateCost = getFullRateInstrCost();
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return (4 * QuarterRateCost + (2 * 2) * FullRateCost) * LT.first * NElts;
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}
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// i32
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return QuarterRateCost * NElts * LT.first;
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}
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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if (SLT == MVT::f64)
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return LT.first * NElts * get64BitInstrCost();
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if (SLT == MVT::f32 || SLT == MVT::f16)
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return LT.first * NElts * getFullRateInstrCost();
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break;
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case ISD::FDIV:
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case ISD::FREM:
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// FIXME: frem should be handled separately. The fdiv in it is most of it,
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// but the current lowering is also not entirely correct.
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if (SLT == MVT::f64) {
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int Cost = 4 * get64BitInstrCost() + 7 * getQuarterRateInstrCost();
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// Add cost of workaround.
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if (ST->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
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Cost += 3 * getFullRateInstrCost();
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return LT.first * Cost * NElts;
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}
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// Assuming no fp32 denormals lowering.
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if (SLT == MVT::f32 || SLT == MVT::f16) {
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assert(!ST->hasFP32Denormals() && "will change when supported");
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int Cost = 7 * getFullRateInstrCost() + 1 * getQuarterRateInstrCost();
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return LT.first * NElts * Cost;
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}
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break;
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default:
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break;
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}
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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}
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unsigned AMDGPUTTIImpl::getCFInstrCost(unsigned Opcode) {
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// XXX - For some reason this isn't called for switch.
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switch (Opcode) {
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case Instruction::Br:
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case Instruction::Ret:
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return 10;
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default:
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return BaseT::getCFInstrCost(Opcode);
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}
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}
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int AMDGPUTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
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unsigned Index) {
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switch (Opcode) {
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case Instruction::ExtractElement:
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case Instruction::InsertElement:
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// Extracts are just reads of a subregister, so are free. Inserts are
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// considered free because we don't want to have any cost for scalarizing
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// operations, and we don't have to copy into a different register class.
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// Dynamic indexing isn't free and is best avoided.
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return Index == ~0u ? 2 : 0;
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default:
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return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
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}
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}
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static bool isIntrinsicSourceOfDivergence(const TargetIntrinsicInfo *TII,
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const IntrinsicInst *I) {
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switch (I->getIntrinsicID()) {
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default:
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return false;
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case Intrinsic::not_intrinsic:
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// This means we have an intrinsic that isn't defined in
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// IntrinsicsAMDGPU.td
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break;
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case Intrinsic::amdgcn_workitem_id_x:
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case Intrinsic::amdgcn_workitem_id_y:
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case Intrinsic::amdgcn_workitem_id_z:
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case Intrinsic::amdgcn_interp_p1:
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case Intrinsic::amdgcn_interp_p2:
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case Intrinsic::amdgcn_mbcnt_hi:
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case Intrinsic::amdgcn_mbcnt_lo:
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case Intrinsic::r600_read_tidig_x:
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case Intrinsic::r600_read_tidig_y:
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case Intrinsic::r600_read_tidig_z:
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case Intrinsic::amdgcn_image_atomic_swap:
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case Intrinsic::amdgcn_image_atomic_add:
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case Intrinsic::amdgcn_image_atomic_sub:
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case Intrinsic::amdgcn_image_atomic_smin:
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case Intrinsic::amdgcn_image_atomic_umin:
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case Intrinsic::amdgcn_image_atomic_smax:
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case Intrinsic::amdgcn_image_atomic_umax:
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case Intrinsic::amdgcn_image_atomic_and:
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case Intrinsic::amdgcn_image_atomic_or:
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case Intrinsic::amdgcn_image_atomic_xor:
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case Intrinsic::amdgcn_image_atomic_inc:
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case Intrinsic::amdgcn_image_atomic_dec:
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case Intrinsic::amdgcn_image_atomic_cmpswap:
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case Intrinsic::amdgcn_buffer_atomic_swap:
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case Intrinsic::amdgcn_buffer_atomic_add:
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case Intrinsic::amdgcn_buffer_atomic_sub:
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case Intrinsic::amdgcn_buffer_atomic_smin:
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case Intrinsic::amdgcn_buffer_atomic_umin:
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case Intrinsic::amdgcn_buffer_atomic_smax:
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case Intrinsic::amdgcn_buffer_atomic_umax:
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case Intrinsic::amdgcn_buffer_atomic_and:
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case Intrinsic::amdgcn_buffer_atomic_or:
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case Intrinsic::amdgcn_buffer_atomic_xor:
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case Intrinsic::amdgcn_buffer_atomic_cmpswap:
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return true;
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}
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StringRef Name = I->getCalledFunction()->getName();
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switch (TII->lookupName((const char *)Name.bytes_begin(), Name.size())) {
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default:
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return false;
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case AMDGPUIntrinsic::SI_tid:
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case AMDGPUIntrinsic::SI_fs_interp:
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return true;
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}
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}
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static bool isArgPassedInSGPR(const Argument *A) {
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const Function *F = A->getParent();
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// Arguments to compute shaders are never a source of divergence.
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if (!AMDGPU::isShader(F->getCallingConv()))
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return true;
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// For non-compute shaders, SGPR inputs are marked with either inreg or byval.
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if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
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F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
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return true;
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// Everything else is in VGPRs.
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return false;
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}
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///
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/// \returns true if the result of the value could potentially be
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/// different across workitems in a wavefront.
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bool AMDGPUTTIImpl::isSourceOfDivergence(const Value *V) const {
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if (const Argument *A = dyn_cast<Argument>(V))
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return !isArgPassedInSGPR(A);
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// Loads from the private address space are divergent, because threads
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// can execute the load instruction with the same inputs and get different
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// results.
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//
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// All other loads are not divergent, because if threads issue loads with the
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// same arguments, they will always get the same result.
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if (const LoadInst *Load = dyn_cast<LoadInst>(V))
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return Load->getPointerAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
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// Atomics are divergent because they are executed sequentially: when an
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// atomic operation refers to the same address in each thread, then each
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// thread after the first sees the value written by the previous thread as
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// original value.
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if (isa<AtomicRMWInst>(V) || isa<AtomicCmpXchgInst>(V))
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return true;
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if (const IntrinsicInst *Intrinsic = dyn_cast<IntrinsicInst>(V)) {
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const TargetMachine &TM = getTLI()->getTargetMachine();
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return isIntrinsicSourceOfDivergence(TM.getIntrinsicInfo(), Intrinsic);
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}
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// Assume all function calls are a source of divergence.
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if (isa<CallInst>(V) || isa<InvokeInst>(V))
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return true;
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return false;
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}
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