llvm-project/llvm/lib
Tim Northover 3657cb0350 ReMat: fix overly cavalier attitude to sub-register indices
There are two attempted optimisations in reMaterializeTrivialDef, trying to
avoid promoting the size of a register too much when rematerializing.
Unfortunately, both appear to be flawed. First, we see if the original register
would have worked, but this is inadequate. Consider:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0 = COPY v1:Q1 (v1, v2 are QQ)
    ...
    uses of v2

In this case even though v2 *could* be used directly as the output of
SOMETHING, this would set the wrong bits of the QQ register involved. The
correct rematerialization must be:

    v2:Q0_Q1 = SOMETHING (v2 promoted to QQQ)
    ...
    uses of v2:Q1_Q2

For the second optimisation, if the correct remat is "v2:idx = SOMETHING" then
we can't necessarily expect v2 itself to be valid for SOMETHING, but we do try
to hunt for a class between v1 and v2 that works. Unfortunately, this is also
wrong:

    v1 = SOMETHING (v1 is QQ)
    v2:Q0_Q1 = COPY v1 (v1 is QQ, v2 is QQQ)
    ...
    uses of v2 as a QQQ

The canonical rematerialization here is "v2:Q0_Q1 = SOMETHING". However current
logic would decide that v2 could be a QQ (no interest is taken in later uses).

This patch, therefore, always accepts the widened register class without trying
to be clever. Generally there is no penalty to this (e.g. in the common GR32 <
GR64 case, expanding the width doesn't matter because it's not like you were
going to do anything else with the high bits of a GR32 register). It can
increase register pressure in cases like the ARM VFP regs though (multiple
non-overlapping but equivalent subregisters). This situation can be
spotted by the fact that both source and destination in the
not-quite-coalesced pair have a sub-register index and
rematerialisation is skipped in that situation.

Unfortunately, no in-tree targets actually expose this as far as I can tell
(there are so few isAsCheapAsAMove instructions for it to trigger on) so I've
been unable to produce a test. It was exposed in our ARM64 SPEC tests though,
and I will be adding a test there that we should be able to contribute
soon(TM).

rdar://problem/15775279

llvm-svn: 199376
2014-01-16 12:29:55 +00:00
..
Analysis BasicAA: We need to check both access sizes when comparing a gep and an 2014-01-16 04:53:18 +00:00
AsmParser Decouple dllexport/dllimport from linkage 2014-01-14 15:22:47 +00:00
Bitcode Make parseBitcodeFile return an ErrorOr<Module *>. 2014-01-15 01:08:23 +00:00
CodeGen ReMat: fix overly cavalier attitude to sub-register indices 2014-01-16 12:29:55 +00:00
DebugInfo llvm-dwarfdump: type unit dwo support 2014-01-09 05:08:24 +00:00
ExecutionEngine Attempt to fix the MSVC build. 2014-01-16 05:09:32 +00:00
IR Report a warning when dropping outdated debug info metadata. 2014-01-16 01:51:12 +00:00
IRReader Make parseBitcodeFile return an ErrorOr<Module *>. 2014-01-15 01:08:23 +00:00
LTO [LTO] Add a hook to map LLVM diagnostics into the clients of LTO. 2014-01-15 22:04:35 +00:00
Linker Reapply r194218 with fix: 2014-01-16 06:29:36 +00:00
MC CommentColumn is always 40. Simplify. 2014-01-16 07:04:11 +00:00
Object llmv-objdump/COFF: Print export table contents. 2014-01-16 07:05:49 +00:00
Option Avoid buffer copies when a Twine already is a StringRef. 2013-12-03 18:18:28 +00:00
Support raw_fd_ostream: Don't change STDERR to O_BINARY, or w*printf() (in assert()) would barf wide chars after llvm::errs(). 2014-01-12 16:14:24 +00:00
TableGen [TableGen] Correctly generate implicit anonymous prototype defs in multiclasses 2014-01-02 20:47:09 +00:00
Target For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback. 2014-01-16 09:16:13 +00:00
Transforms [asan] Remove -fsanitize-address-zero-base-shadow command line 2014-01-16 10:19:12 +00:00
CMakeLists.txt Move LTO support library to a component, allowing it to be tested 2013-09-24 23:52:22 +00:00
LLVMBuild.txt Move LTO support library to a component, allowing it to be tested 2013-09-24 23:52:22 +00:00
Makefile Reformat Makefile. No other changes. 2013-10-30 04:03:03 +00:00