maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Kerry McLaughlin e55b3bf40e [SVE][Inline-Asm] Add constraints for SVE predicate registers 
Summary:
Adds the following inline asm constraints for SVE:
  - Upl: One of the low eight SVE predicate registers, P0 to P7 inclusive
  - Upa: SVE predicate register with full range, P0 to P15

Reviewers: t.p.northover, sdesmalen, rovka, momchil.velikov, cameron.mcinally, greened, rengolin

Reviewed By: rovka

Subscribers: javed.absar, tschuett, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66524

llvm-svn: 371967
 		2019-09-16 09:45:27 +00:00
..
AArch64 [SVE][Inline-Asm] Add constraints for SVE predicate registers 2019-09-16 09:45:27 +00:00
AMDGPU AMDGPU/GlobalISel: Remove illegal select tests 2019-09-16 04:21:10 +00:00
ARC
…
ARM [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
AVR
…
BPF [BPF] Fix bpf llvm-objdump issues. 2019-08-17 22:12:00 +00:00
Generic Revert "Reland "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."" 2019-09-10 10:39:09 +00:00
Hexagon [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Inputs
…
Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
MSP430
…
Mips [MIPS GlobalISel] Select indirect branch 2019-09-12 11:44:36 +00:00
NVPTX [NVPTX] Fix PR41651 2019-07-30 19:52:01 +00:00
PowerPC [PowerPC][NFC] Add a testcase for fdiv expansion. 2019-09-15 20:02:25 +00:00
RISCV [RISCV] Support stack offset exceed 32-bit for RV64 2019-09-13 04:03:32 +00:00
SPARC [test] Fix tests when run on windows after SVN r369426. NFC. 2019-08-20 20:58:02 +00:00
SystemZ [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Thumb [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Thumb2 [ARM] Masked loads and stores 2019-09-15 14:14:47 +00:00
WebAssembly [WebAssembly] Narrowing and widening SIMD ops 2019-09-13 22:54:41 +00:00
WinCFGuard
…
WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support. 2019-09-14 16:38:26 +00:00
XCore
…