forked from OSchip/llvm-project
103 lines
3.8 KiB
C++
103 lines
3.8 KiB
C++
//===--------------------- Backend.h ----------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements an OoO backend for the llvm-mca tool.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#define LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#include "DispatchStage.h"
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#include "FetchStage.h"
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#include "InstrBuilder.h"
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#include "RegisterFile.h"
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#include "RetireControlUnit.h"
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#include "RetireStage.h"
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#include "Scheduler.h"
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namespace mca {
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class HWEventListener;
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class HWInstructionEvent;
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class HWStallEvent;
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/// An out of order backend for a specific subtarget.
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///
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/// It emulates an out-of-order execution of instructions. Instructions are
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/// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
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/// Instructions are firstly fetched, then dispatched to the schedulers, and
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/// then executed.
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///
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/// This class tracks the lifetime of an instruction from the moment where
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/// it gets dispatched to the schedulers, to the moment where it finishes
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/// executing and register writes are architecturally committed.
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/// In particular, it monitors changes in the state of every instruction
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/// in flight.
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///
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/// Instructions are executed in a loop of iterations. The number of iterations
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/// is defined by the SourceMgr object, which is managed by the initial stage
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/// of the instruction pipeline.
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///
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/// The Backend entry point is method 'run()' which executes cycles in a loop
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/// until there are new instructions to dispatch, and not every instruction
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/// has been retired.
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///
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/// Internally, the Backend collects statistical information in the form of
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/// histograms. For example, it tracks how the dispatch group size changes
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/// over time.
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class Backend {
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// The following are the simulated hardware components of the backend.
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RetireControlUnit RCU;
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RegisterFile PRF;
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/// TODO: Eventually this will become a list of unique Stage* that this
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/// backend pipeline executes.
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std::unique_ptr<FetchStage> Fetch;
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std::unique_ptr<Scheduler> HWS;
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std::unique_ptr<DispatchStage> Dispatch;
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std::unique_ptr<RetireStage> Retire;
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std::set<HWEventListener *> Listeners;
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unsigned Cycles;
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void runCycle(unsigned Cycle);
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public:
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Backend(const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI,
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std::unique_ptr<FetchStage> InitialStage, unsigned DispatchWidth = 0,
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unsigned RegisterFileSize = 0, unsigned LoadQueueSize = 0,
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unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
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: RCU(Subtarget.getSchedModel()),
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PRF(Subtarget.getSchedModel(), MRI, RegisterFileSize),
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Fetch(std::move(InitialStage)),
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HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(), RCU,
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LoadQueueSize, StoreQueueSize,
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AssumeNoAlias)),
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Dispatch(llvm::make_unique<DispatchStage>(
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this, Subtarget, MRI, RegisterFileSize, DispatchWidth, RCU, PRF,
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HWS.get())),
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Retire(llvm::make_unique<RetireStage>(this, RCU, PRF)), Cycles(0) {}
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void run();
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void addEventListener(HWEventListener *Listener);
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void notifyCycleBegin(unsigned Cycle);
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void notifyInstructionEvent(const HWInstructionEvent &Event);
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void notifyStallEvent(const HWStallEvent &Event);
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void notifyResourceAvailable(const ResourceRef &RR);
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void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyCycleEnd(unsigned Cycle);
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};
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} // namespace mca
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#endif
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