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llvm-project/llvm/test/CodeGen
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Craig Topper c562fae02b [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. 
If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead.

The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this.

Differential Revision: https://reviews.llvm.org/D56156

llvm-svn: 350235
 		2019-01-02 17:58:27 +00:00
..
AArch64 Reversing the commit in revision 350186. Revision causes regression in 4 2019-01-01 07:28:55 +00:00
AMDGPU [AMDGPU] Handle OR as operand of raw load/store 2019-01-02 09:47:41 +00:00
ARC
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ARM [ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR. 2018-12-21 18:07:10 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF [BPF] Generate BTF DebugInfo under BPF target 2018-12-19 16:40:25 +00:00
Generic Move llc-start-stop-instance to x86 2018-12-04 18:19:08 +00:00
Hexagon [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
Inputs
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Lanai [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
MIR [Dwarf/AArch64] Return address signing B key dwarf support 2018-12-21 10:45:08 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [MIPS GlobalISel] Select G_SELECT 2018-12-25 14:42:30 +00:00
NVPTX [NVPTX] Allow libcalls that are defined in the current module. 2018-12-26 19:12:31 +00:00
Nios2
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PowerPC [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. 2019-01-02 17:58:27 +00:00
RISCV [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
SPARC [Sparc] Use float register for integer constrained with "f" in inline asm 2018-12-13 15:13:29 +00:00
SystemZ [SystemZ] Make better use of VLLEZ 2018-12-20 13:05:03 +00:00
Thumb [ARM] Complete the Thumb1 shift+and->shift+shift transforms. 2018-12-20 23:39:54 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] Fix invalid machine instrs in -O0, verify in tests 2018-12-21 06:58:15 +00:00
WinCFGuard
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WinEH
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X86 [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them. 2019-01-02 17:58:27 +00:00
XCore [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00