llvm-project/llvm/test/MC/Disassembler
Craig Topper 82974e0114 [X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix.
The 0xf3 prefix has been defined as wbnoinvd on Icelake Server. So
the prefix isn't ignored by the CPU. AMD documentation suggests that
wbnoinvd is treated as wbinvd on older processors. Intel documentation
is not clear. Perhaps 0xf2 and 0x66 are treated the same, but its
not documented.

This patch changes TB to PS in the td file so 0xf2 and 0x66 will
be treated as errors. This matches versions of objdump after
wbnoinvd was added.
2020-10-25 20:56:01 -07:00
..
AArch64 [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM 2020-07-10 18:24:11 +01:00
AMDGPU [AMDGPU] flat scratch ST addressing mode on gfx10 2020-10-19 15:29:52 -07:00
ARC
ARM [ARM] Fix Asm/Disasm of TBB/TBH instructions 2020-07-22 09:31:56 +01:00
Hexagon
Lanai
MSP430
Mips [mips] Implement Octeon+ `saa` and `saad` instructions 2019-11-07 13:58:50 +03:00
PowerPC [PowerPC] Add outer product instructions for MMA 2020-09-30 18:06:49 -05:00
RISCV [RISCV] Implement evaluateBranch 2020-04-09 15:11:55 +01:00
Sparc
SystemZ [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
WebAssembly [WebAssembly] Renumber SIMD opcodes 2020-05-01 17:20:49 -07:00
X86 [X86] Don't disassemble wbinvd with 0xf2 or 0x66 prefix. 2020-10-25 20:56:01 -07:00
XCore