forked from OSchip/llvm-project
91 lines
2.8 KiB
TeX
Executable File
91 lines
2.8 KiB
TeX
Executable File
% Latex header for doxygen 1.8.3.1
|
|
\documentclass{book}
|
|
\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
|
|
\usepackage{makeidx}
|
|
\usepackage{natbib}
|
|
\usepackage{graphicx}
|
|
\usepackage{multicol}
|
|
\usepackage{float}
|
|
\usepackage{listings}
|
|
\usepackage{color}
|
|
\usepackage{ifthen}
|
|
\usepackage[table]{xcolor}
|
|
\usepackage{textcomp}
|
|
\usepackage{alltt}
|
|
\usepackage{ifpdf}
|
|
\ifpdf
|
|
\usepackage[pdftex,
|
|
pagebackref=true,
|
|
colorlinks=true,
|
|
linkcolor=blue,
|
|
unicode
|
|
]{hyperref}
|
|
\else
|
|
\usepackage[ps2pdf,
|
|
pagebackref=true,
|
|
colorlinks=true,
|
|
linkcolor=blue,
|
|
unicode
|
|
]{hyperref}
|
|
\usepackage{pspicture}
|
|
\fi
|
|
\usepackage[utf8]{inputenc}
|
|
\usepackage{mathptmx}
|
|
\usepackage[scaled=.90]{helvet}
|
|
\usepackage{courier}
|
|
\usepackage{sectsty}
|
|
\usepackage{amssymb}
|
|
\usepackage[titles]{tocloft}
|
|
\usepackage{doxygen}
|
|
\usepackage{fancyhdr}
|
|
\pagestyle{fancy}
|
|
\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
|
|
\makeindex
|
|
\setcounter{tocdepth}{3}
|
|
\renewcommand{\footrulewidth}{0.4pt}
|
|
\renewcommand{\familydefault}{\sfdefault}
|
|
\hfuzz=15pt
|
|
\setlength{\emergencystretch}{15pt}
|
|
\hbadness=750
|
|
\tolerance=750
|
|
\begin{document}
|
|
\hypersetup{pageanchor=false,citecolor=blue}
|
|
\begin{titlepage}
|
|
\vspace*{7cm}
|
|
\begin{center}
|
|
{\Large Intel\textsuperscript{\textregistered} Offload Runtime Library }\\
|
|
\vspace*{1cm}
|
|
{\large Generated by Doxygen $doxygenversion }\\
|
|
\vspace*{0.5cm}
|
|
{\small $datetime }\\
|
|
\end{center}
|
|
\end{titlepage}
|
|
|
|
{\bf FTC Optimization Notice}
|
|
|
|
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for
|
|
optimizations that are not unique to Intel microprocessors. These optimizations include SSE2,
|
|
SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the
|
|
availability, functionality, or effectiveness of any optimization on microprocessors not
|
|
manufactured by Intel.
|
|
|
|
Microprocessor-dependent optimizations in this product are intended for use with Intel
|
|
microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for
|
|
Intel microprocessors. Please refer to the applicable product User and Reference Guides for
|
|
more information regarding the specific instruction sets covered by this notice.
|
|
|
|
Notice revision \#20110804
|
|
|
|
\vspace*{0.5cm}
|
|
|
|
{\bf Trademarks}
|
|
|
|
Intel, Xeon, and Intel Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries.
|
|
|
|
This document is Copyright \textcopyright 2014, Intel Corporation. All rights reserved.
|
|
|
|
\pagenumbering{roman}
|
|
\tableofcontents
|
|
\pagenumbering{arabic}
|
|
\hypersetup{pageanchor=true,citecolor=blue}
|