forked from OSchip/llvm-project
104 lines
2.7 KiB
C++
104 lines
2.7 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include <stdio.h>
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm, *this)
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{ }
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const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const
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{
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return RI;
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}
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const
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{
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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unsigned SIInstrInfo::getEncodingType(const MachineInstr &MI) const
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{
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return get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
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}
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unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
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{
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/* Instructions with literal constants are expanded to 64-bits, and
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* the constant is stored in bits [63:32] */
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for (unsigned i = 0; i < MI.getNumOperands(); i++) {
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if (MI.getOperand(i).getType() == MachineOperand::MO_FPImmediate) {
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return 8;
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}
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}
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/* This instruction always has a literal */
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if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
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return 8;
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}
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unsigned encoding_type = getEncodingType(MI);
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switch (encoding_type) {
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case SIInstrEncodingType::EXP:
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case SIInstrEncodingType::LDS:
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case SIInstrEncodingType::MUBUF:
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case SIInstrEncodingType::MTBUF:
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case SIInstrEncodingType::MIMG:
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case SIInstrEncodingType::VOP3:
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return 8;
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default:
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return 4;
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}
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}
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MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const
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{
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
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MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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MachineInstrBuilder(MI).addImm(Imm);
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return MI;
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const
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{
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I32:
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return true;
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}
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}
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