forked from OSchip/llvm-project
76 lines
2.0 KiB
C++
76 lines
2.0 KiB
C++
//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Interface definition for R600InstrInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600INSTRUCTIONINFO_H_
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#define R600INSTRUCTIONINFO_H_
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#include "AMDIL.h"
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#include "AMDILInstrInfo.h"
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#include "R600RegisterInfo.h"
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#include <map>
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namespace llvm {
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class AMDGPUTargetMachine;
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class DFAPacketizer;
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class ScheduleDAG;
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class MachineFunction;
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class MachineInstr;
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class MachineInstrBuilder;
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class R600InstrInfo : public AMDGPUInstrInfo {
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private:
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const R600RegisterInfo RI;
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public:
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explicit R600InstrInfo(AMDGPUTargetMachine &tm);
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const R600RegisterInfo &getRegisterInfo() const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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bool isTrig(const MachineInstr &MI) const;
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/// isVector - Vector instructions are instructions that must fill all
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/// instruction slots within an instruction group.
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bool isVector(const MachineInstr &MI) const;
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virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const;
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virtual unsigned getIEQOpcode() const;
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virtual bool isMov(unsigned Opcode) const;
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DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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};
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} // End llvm namespace
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namespace R600_InstFlag {
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enum TIF {
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TRANS_ONLY = (1 << 0),
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TEX = (1 << 1),
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REDUCTION = (1 << 2),
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FC = (1 << 3),
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TRIG = (1 << 4),
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OP3 = (1 << 5),
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VECTOR = (1 << 6)
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};
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}
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#endif // R600INSTRINFO_H_
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