forked from OSchip/llvm-project
394 lines
12 KiB
C++
394 lines
12 KiB
C++
//===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the AMDIL target.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h" // For AMDGPUISD
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#include "AMDILDevices.h"
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#include "AMDILUtilityFunctions.h"
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#include "llvm/ADT/ValueMap.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Support/Compiler.h"
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#include <list>
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#include <queue>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMDILDAGToDAGISel - AMDIL specific code to select AMDIL machine instructions
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// //for SelectionDAG operations.
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//
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namespace {
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class AMDILDAGToDAGISel : public SelectionDAGISel {
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// Subtarget - Keep a pointer to the AMDIL Subtarget around so that we can
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// make the right decision when generating code for different targets.
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const AMDILSubtarget &Subtarget;
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public:
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AMDILDAGToDAGISel(TargetMachine &TM AMDIL_OPT_LEVEL_DECL);
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virtual ~AMDILDAGToDAGISel();
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SDNode *Select(SDNode *N);
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virtual const char *getPassName() const;
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private:
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inline SDValue getSmallIPtrImm(unsigned Imm);
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// Complex pattern selectors
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bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
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bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
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static bool checkType(const Value *ptr, unsigned int addrspace);
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static const Value *getBasePointerValue(const Value *V);
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static bool isGlobalStore(const StoreSDNode *N);
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static bool isPrivateStore(const StoreSDNode *N);
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static bool isLocalStore(const StoreSDNode *N);
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static bool isRegionStore(const StoreSDNode *N);
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static bool isCPLoad(const LoadSDNode *N);
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static bool isConstantLoad(const LoadSDNode *N, int cbID);
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static bool isGlobalLoad(const LoadSDNode *N);
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static bool isPrivateLoad(const LoadSDNode *N);
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static bool isLocalLoad(const LoadSDNode *N);
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static bool isRegionLoad(const LoadSDNode *N);
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bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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} // end anonymous namespace
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// createAMDILISelDag - This pass converts a legalized DAG into a AMDIL-specific
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// DAG, ready for instruction scheduling.
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//
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FunctionPass *llvm::createAMDILISelDag(TargetMachine &TM
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AMDIL_OPT_LEVEL_DECL) {
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return new AMDILDAGToDAGISel(TM AMDIL_OPT_LEVEL_VAR);
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}
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AMDILDAGToDAGISel::AMDILDAGToDAGISel(TargetMachine &TM
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AMDIL_OPT_LEVEL_DECL)
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: SelectionDAGISel(TM AMDIL_OPT_LEVEL_VAR), Subtarget(TM.getSubtarget<AMDILSubtarget>())
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{
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}
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AMDILDAGToDAGISel::~AMDILDAGToDAGISel() {
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}
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SDValue AMDILDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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bool AMDILDAGToDAGISel::SelectADDRParam(
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SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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return true;
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}
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bool AMDILDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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return SelectADDRParam(Addr, R1, R2);
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}
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bool AMDILDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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return true;
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}
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SDNode *AMDILDAGToDAGISel::Select(SDNode *N) {
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unsigned int Opc = N->getOpcode();
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if (N->isMachineOpcode()) {
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return NULL; // Already selected.
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}
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switch (Opc) {
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default: break;
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case ISD::FrameIndex:
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{
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
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unsigned int FI = FIN->getIndex();
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EVT OpVT = N->getValueType(0);
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unsigned int NewOpc = AMDGPU::COPY;
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
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return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI);
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}
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}
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break;
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}
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return SelectCode(N);
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}
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bool AMDILDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
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if (!ptr) {
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return false;
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}
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Type *ptrType = ptr->getType();
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return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
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}
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const Value * AMDILDAGToDAGISel::getBasePointerValue(const Value *V)
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{
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if (!V) {
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return NULL;
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}
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const Value *ret = NULL;
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ValueMap<const Value *, bool> ValueBitMap;
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std::queue<const Value *, std::list<const Value *> > ValueQueue;
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ValueQueue.push(V);
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while (!ValueQueue.empty()) {
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V = ValueQueue.front();
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if (ValueBitMap.find(V) == ValueBitMap.end()) {
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ValueBitMap[V] = true;
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if (dyn_cast<Argument>(V) && dyn_cast<PointerType>(V->getType())) {
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ret = V;
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break;
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} else if (dyn_cast<GlobalVariable>(V)) {
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ret = V;
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break;
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} else if (dyn_cast<Constant>(V)) {
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const ConstantExpr *CE = dyn_cast<ConstantExpr>(V);
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if (CE) {
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ValueQueue.push(CE->getOperand(0));
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}
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} else if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
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ret = AI;
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break;
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} else if (const Instruction *I = dyn_cast<Instruction>(V)) {
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uint32_t numOps = I->getNumOperands();
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for (uint32_t x = 0; x < numOps; ++x) {
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ValueQueue.push(I->getOperand(x));
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}
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} else {
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// assert(0 && "Found a Value that we didn't know how to handle!");
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}
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}
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ValueQueue.pop();
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}
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return ret;
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}
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bool AMDILDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
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return (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS));
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}
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bool AMDILDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int cbID) {
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if (checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)) {
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return true;
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}
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MachineMemOperand *MMO = N->getMemOperand();
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const Value *V = MMO->getValue();
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const Value *BV = getBasePointerValue(V);
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if (MMO
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&& MMO->getValue()
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&& ((V && dyn_cast<GlobalValue>(V))
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|| (BV && dyn_cast<GlobalValue>(
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getBasePointerValue(MMO->getValue()))))) {
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return checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS);
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} else {
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return false;
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}
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}
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bool AMDILDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isLocalLoad(const LoadSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isRegionLoad(const LoadSDNode *N) {
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return checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS);
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}
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bool AMDILDAGToDAGISel::isCPLoad(const LoadSDNode *N) {
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MachineMemOperand *MMO = N->getMemOperand();
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if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
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if (MMO) {
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const Value *V = MMO->getValue();
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const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
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if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
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return true;
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}
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}
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}
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return false;
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}
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bool AMDILDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) {
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if (checkType(N->getSrcValue(), AMDILAS::PRIVATE_ADDRESS)) {
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// Check to make sure we are not a constant pool load or a constant load
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// that is marked as a private load
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if (isCPLoad(N) || isConstantLoad(N, -1)) {
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return false;
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}
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}
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if (!checkType(N->getSrcValue(), AMDILAS::LOCAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::GLOBAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::REGION_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::CONSTANT_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::PARAM_D_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDILAS::PARAM_I_ADDRESS))
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{
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return true;
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}
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return false;
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}
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const char *AMDILDAGToDAGISel::getPassName() const {
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return "AMDIL DAG->DAG Pattern Instruction Selection";
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}
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#ifdef DEBUGTMP
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#undef INT64_C
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#endif
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#undef DEBUGTMP
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///==== AMDGPU Functions ====///
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bool AMDILDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
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SDValue& Offset) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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bool Match = false;
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// Find the base ptr and the offset
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for (unsigned i = 0; i < Addr.getNumOperands(); i++) {
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SDValue Arg = Addr.getOperand(i);
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ConstantSDNode * OffsetNode = dyn_cast<ConstantSDNode>(Arg);
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// This arg isn't a constant so it must be the base PTR.
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if (!OffsetNode) {
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Base = Addr.getOperand(i);
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continue;
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}
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// Check if the constant argument fits in 8-bits. The offset is in bytes
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// so we need to convert it to dwords.
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if (isInt<8>(OffsetNode->getZExtValue() >> 2)) {
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Match = true;
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Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
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MVT::i32);
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}
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}
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return Match;
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}
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// Default case, no offset
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool AMDILDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
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SDValue &Offset)
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{
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ConstantSDNode * IMMOffset;
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if (Addr.getOpcode() == ISD::ADD
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&& (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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&& isInt<16>(IMMOffset->getZExtValue())) {
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
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return true;
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// If the pointer address is constant, we can move it to the offset field.
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} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
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&& isInt<16>(IMMOffset->getZExtValue())) {
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Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
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CurDAG->getEntryNode().getDebugLoc(),
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AMDGPU::ZERO, MVT::i32);
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Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
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return true;
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}
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// Default case, no offset
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool AMDILDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
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SDValue& Offset) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() != ISD::ADD) {
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return false;
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}
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return false;
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}
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