forked from OSchip/llvm-project
114 lines
4.0 KiB
TableGen
114 lines
4.0 KiB
TableGen
//===- AMDIL.td - AMDIL Target Machine -------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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// Dummy Instruction itineraries for pseudo instructions
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def ALU_NULL : FuncUnit;
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def NullALU : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// AMDIL Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureFP64 : SubtargetFeature<"fp64",
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"CapsOverride[AMDILDeviceInfo::DoubleOps]",
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"true",
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"Enable 64bit double precision operations">;
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def FeatureByteAddress : SubtargetFeature<"byte_addressable_store",
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"CapsOverride[AMDILDeviceInfo::ByteStores]",
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"true",
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"Enable byte addressable stores">;
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def FeatureBarrierDetect : SubtargetFeature<"barrier_detect",
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"CapsOverride[AMDILDeviceInfo::BarrierDetect]",
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"true",
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"Enable duplicate barrier detection(HD5XXX or later).">;
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def FeatureImages : SubtargetFeature<"images",
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"CapsOverride[AMDILDeviceInfo::Images]",
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"true",
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"Enable image functions">;
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def FeatureMultiUAV : SubtargetFeature<"multi_uav",
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"CapsOverride[AMDILDeviceInfo::MultiUAV]",
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"true",
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"Generate multiple UAV code(HD5XXX family or later)">;
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def FeatureMacroDB : SubtargetFeature<"macrodb",
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"CapsOverride[AMDILDeviceInfo::MacroDB]",
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"true",
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"Use internal macrodb, instead of macrodb in driver">;
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def FeatureNoAlias : SubtargetFeature<"noalias",
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"CapsOverride[AMDILDeviceInfo::NoAlias]",
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"true",
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"assert that all kernel argument pointers are not aliased">;
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def FeatureNoInline : SubtargetFeature<"no-inline",
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"CapsOverride[AMDILDeviceInfo::NoInline]",
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"true",
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"specify whether to not inline functions">;
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def Feature64BitPtr : SubtargetFeature<"64BitPtr",
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"mIs64bit",
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"false",
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"Specify if 64bit addressing should be used.">;
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def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
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"mIs32on64bit",
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"false",
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"Specify if 64bit sized pointers with 32bit addressing should be used.">;
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def FeatureDebug : SubtargetFeature<"debug",
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"CapsOverride[AMDILDeviceInfo::Debug]",
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"true",
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"Debug mode is enabled, so disable hardware accelerated address spaces.">;
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def FeatureDumpCode : SubtargetFeature <"DumpCode",
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"mDumpCode",
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"true",
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"Dump MachineInstrs in the CodeEmitter">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AMDILRegisterInfo.td"
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include "AMDILCallingConv.td"
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include "AMDILInstrInfo.td"
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def AMDILInstrInfo : InstrInfo {}
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//===----------------------------------------------------------------------===//
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// AMDIL processors supported.
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//===----------------------------------------------------------------------===//
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//include "Processors.td"
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def AMDILAsmWriter : AsmWriter {
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string AsmWriterClassName = "AsmPrinter";
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int Variant = 0;
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}
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def AMDILAsmParser : AsmParser {
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string AsmParserClassName = "AsmParser";
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int Variant = 0;
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string CommentDelimiter = ";";
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string RegisterPrefix = "r";
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}
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def AMDIL : Target {
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// Pull in Instruction Info:
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let InstructionSet = AMDILInstrInfo;
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let AssemblyWriters = [AMDILAsmWriter];
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let AssemblyParsers = [AMDILAsmParser];
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}
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