llvm-project/llvm/test/CodeGen
Nicolai Haehnle c4a2ff0950 AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
Summary:
Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
the load is really uniform. So select the scalar load intrinsics directly
to either VMEM or SMRD buffer loads based on divergence analysis.

If an offset happens to end up in a VGPR -- either because a floating
point calculation was involved, or due to other remaining deficiencies
in SIFixSGPRCopies -- we use v_readfirstlane.

There is some unrelated churn in tests since we now select MUBUF offsets
in a unified way with non-scalar buffer loads.

Change-Id: I170e6816323beb1348677b358c9d380865cd1a19

Reviewers: arsenm, alex-t, rampitec, tpr

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D53283

llvm-svn: 344696
2018-10-17 15:37:30 +00:00
..
AArch64 [AARCH64] Improve vector popcnt lowering with ADDLP 2018-10-15 21:15:58 +00:00
AMDGPU AMDGPU: Divergence-driven selection of scalar buffer load intrinsics 2018-10-17 15:37:30 +00:00
ARC
ARM [ARM] bottom-top mul support in ARMParallelDSP 2018-10-17 13:02:48 +00:00
AVR [AVR] Fix the 'call.ll' CodeGen test 2018-10-10 03:21:42 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic Revert r344197 "[MC][ELF] compute entity size for explicit sections" 2018-10-11 18:43:08 +00:00
Hexagon [TwoAddressInstructionPass] Replace subregister uses when processing tied operands 2018-10-15 08:36:03 +00:00
Inputs
Lanai
MIR [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL 2018-10-01 21:59:45 +00:00
MSP430 [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Mips [MIPS GlobalISel] Legalize constants 2018-10-17 10:30:03 +00:00
NVPTX [NVPTX] Implement isLegalToVectorizeLoadChain 2018-08-27 17:29:43 +00:00
Nios2
PowerPC [PowerPC] avoid masking already-zero bits in BitPermutationSelector 2018-10-12 14:02:20 +00:00
RISCV [RISCV] Eliminate unnecessary masking of promoted shift amounts 2018-10-12 23:18:52 +00:00
SPARC [Sparc] Remove the support for builtin setjmp/longjmp 2018-09-27 13:32:54 +00:00
SystemZ [DAGCombine] Improve Load-Store Forwarding 2018-10-10 14:15:52 +00:00
Thumb Revert "Revert "[ConstHoist] Do not rebase single (or few) dependent constant"" 2018-09-26 00:59:09 +00:00
Thumb2 [ARM] Do not fuse VADD and VMUL on the Cortex-M4 and Cortex-M33 2018-09-24 12:02:50 +00:00
WebAssembly Revert "[WebAssembly] LSDA info generation" 2018-10-16 18:50:09 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
X86 [X86] Match (cmp (and (shr X, C), mask), 0) to BEXTR+TEST. 2018-10-16 22:29:36 +00:00
XCore