llvm-project/llvm/lib/CodeGen
Jakub Staszak ec5a2f248f Use dyn_cast instead of isa and cast.
No functionality change.

llvm-svn: 164924
2012-09-30 21:24:57 +00:00
..
AsmPrinter Mark jump tables in code sections with DataRegion directives. 2012-09-24 23:06:27 +00:00
SelectionDAG Use dyn_cast instead of isa and cast. 2012-09-30 21:24:57 +00:00
AggressiveAntiDepBreaker.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AggressiveAntiDepBreaker.h Rename TargetSubtarget to TargetSubtargetInfo for consistency. 2011-07-01 21:01:15 +00:00
AllocationOrder.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
AllocationOrder.h Fix old doxygen comment. 2012-01-24 18:09:18 +00:00
Analysis.cpp Convert some attribute existence queries over to use the predicate methods. 2012-09-19 23:54:18 +00:00
AntiDepBreaker.h
BranchFolding.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
BranchFolding.h When tail-merging multiple blocks, make sure to correctly update the live-in list on the merged block to correctly account for the live-outs of all the predecessors. They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF). 2011-07-06 23:41:48 +00:00
CMakeLists.txt Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CalcSpillWeights.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
CallingConvLower.cpp Add an ensureMaxAlignment() function to MachineFrameInfo (analogous to 2012-06-19 22:59:12 +00:00
CodeGen.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
CodePlacementOpt.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
CriticalAntiDepBreaker.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
CriticalAntiDepBreaker.h Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
DFAPacketizer.cpp Revert r158679 - use case is unclear (and it increases the memory footprint). 2012-06-22 20:27:13 +00:00
DeadMachineInstructionElim.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
DwarfEHPrepare.cpp Relax the requirement that the exception object must be an instruction. During 2012-05-17 17:59:51 +00:00
EarlyIfConversion.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
EdgeBundles.cpp Twinify GraphWriter a little bit. 2011-11-15 16:26:38 +00:00
ExecutionDepsFix.cpp Fix typos found by http://github.com/lyda/misspell-check 2012-06-02 10:20:22 +00:00
ExpandISelPseudos.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
ExpandPostRAPseudos.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
GCMetadata.cpp Add 'llvm_unreachable' to passify GCC's understanding of the constraints 2012-01-10 18:08:01 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 2012-02-19 11:37:01 +00:00
IfConversion.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
InlineSpiller.cpp Add an analyzePhysReg() function to MachineOperandIteratorBase that analyses an instruction's use of a physical register, analogous to analyzeVirtReg. 2012-09-12 10:03:31 +00:00
InterferenceCache.cpp Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
InterferenceCache.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
IntrinsicLowering.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
JITCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
LLVMTargetMachine.cpp When creating MCAsmBackend pass the CPU string as well. In X86AsmBackend 2012-09-18 16:08:49 +00:00
LatencyPriorityQueue.cpp misched preparation: rename core scheduler methods for consistency. 2012-03-07 23:00:49 +00:00
LexicalScopes.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
LiveDebugVariables.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
LiveDebugVariables.h
LiveInterval.cpp Don't dereference begin() on an empty vector. 2012-09-27 21:05:59 +00:00
LiveIntervalAnalysis.cpp Extend -new-coalescer SSA update to handle mapped values as well. 2012-09-20 23:08:39 +00:00
LiveIntervalUnion.cpp Move LiveUnionArray into LiveIntervalUnion.h 2012-06-05 23:57:30 +00:00
LiveIntervalUnion.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00
LiveRangeCalc.cpp Clear kill flags while computing live ranges. 2012-09-06 18:15:15 +00:00
LiveRangeCalc.h Be more verbose when detecting dominance problems. 2012-07-13 23:39:05 +00:00
LiveRangeEdit.cpp Avoid dereferencing a NULL pointer. 2012-09-27 16:34:19 +00:00
LiveRegMatrix.cpp Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
LiveRegMatrix.h comment typo 2012-09-18 22:57:42 +00:00
LiveStackAnalysis.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
LiveVariables.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
LocalStackSlotAllocation.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
MachineBasicBlock.cpp Add a function computeRegisterLiveness() to MachineBasicBlock. This uses analyzePhysReg() from r163694 to heuristically try and determine the liveness state of a physical register upon arrival at a particular instruction in a block. 2012-09-12 10:18:23 +00:00
MachineBlockFrequencyInfo.cpp Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 2011-12-20 20:03:10 +00:00
MachineBlockPlacement.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
MachineBranchProbabilityInfo.cpp Fix a quadratic algorithm in MachineBranchProbabilityInfo. 2012-08-20 22:01:38 +00:00
MachineCSE.cpp MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already. 2012-08-11 20:42:59 +00:00
MachineCodeEmitter.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
MachineCopyPropagation.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
MachineDominators.cpp
MachineFunction.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
MachineFunctionAnalysis.cpp Sink codegen optimization level into MCCodeGenInfo along side relocation model 2011-11-16 08:38:26 +00:00
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Print SlotIndexes when available for -print-machineinstrs. 2012-07-04 23:53:19 +00:00
MachineInstr.cpp Fix PR11985 2012-09-12 21:43:09 +00:00
MachineInstrBundle.cpp Increase the static sizes of some SmallSets. finalizeBundle() is very frequently called for some backends, and growing into an std::set is overkill for these numbers. 2012-09-17 18:31:15 +00:00
MachineLICM.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
MachineLoopInfo.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
MachineLoopRanges.cpp
MachineModuleInfo.cpp Properly emit _fltused with FastISel. Refactor to share code with SDAG. 2012-02-22 19:06:13 +00:00
MachineModuleInfoImpls.cpp Rename virtual table anchors from Anchor() to anchor() for consistency with the rest of the tree. 2012-09-26 06:36:36 +00:00
MachinePassRegistry.cpp Allow targets to select the default scheduler by name. 2012-04-19 01:34:10 +00:00
MachinePostDominators.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
MachineRegisterInfo.cpp Reapply r161633-161634 "Partition use lists so defs always come before uses."" 2012-08-10 00:21:30 +00:00
MachineSSAUpdater.cpp Fix undefined behavior: binding null pointer to reference. No functionality change. 2012-08-14 05:31:26 +00:00
MachineScheduler.cpp misched: add a hook for custom DAG postprocessing. 2012-09-14 17:22:42 +00:00
MachineSink.cpp MachineSink: Sort the successors before trying to find SuccToSinkTo. 2012-07-31 20:45:38 +00:00
MachineTraceMetrics.cpp Give MachineTraceMetrics its own debug tag. 2012-08-10 22:27:29 +00:00
MachineTraceMetrics.h Add more trace query functions. 2012-08-10 22:27:27 +00:00
MachineVerifier.cpp Stop casting away const qualifier needlessly. 2012-09-05 22:26:57 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
PHIElimination.cpp Split loop exiting edges more aggressively. 2012-07-20 20:49:53 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
Passes.cpp Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 2012-09-06 09:17:37 +00:00
PeepholeOptimizer.cpp Use standard pattern for iterate+erase. 2012-08-17 14:38:59 +00:00
PostRASchedulerList.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ProcessImplicitDefs.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
PrologEpilogInserter.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
PrologEpilogInserter.h Codegen pass definition cleanup. No functionality. 2012-02-08 21:23:13 +00:00
PseudoSourceValue.cpp More dead code removal (using -Wunreachable-code) 2012-01-20 21:51:11 +00:00
README.txt
RegAllocBase.cpp Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBase.h Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBasic.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocFast.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocGreedy.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
RegAllocPBQP.cpp Remove unused typedefs gcc4.8 warns about. 2012-09-05 17:55:46 +00:00
RegisterClassInfo.cpp Move RegisterClassInfo.h. 2012-06-06 20:29:31 +00:00
RegisterCoalescer.cpp Remove <def,read-undef> flags from partial redefinitions. 2012-09-27 23:31:32 +00:00
RegisterCoalescer.h Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
RegisterPressure.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
RegisterScavenging.cpp Switch all register list clients to the new MC*Iterator interface. 2012-06-01 23:28:30 +00:00
ScheduleDAG.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ScheduleDAGInstrs.cpp misched: Make ScheduleDAGInstrs use the TargetSchedule interface. 2012-09-18 18:20:00 +00:00
ScheduleDAGPrinter.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
ScoreboardHazardRecognizer.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
ShadowStackGC.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
ShrinkWrapping.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
SjLjEHPrepare.cpp IRBuilderify the SjlLjEHPrepare pass. 2012-09-03 12:27:43 +00:00
SlotIndexes.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
SpillPlacement.cpp Give a small negative bias to giant edge bundles. 2012-05-21 03:11:23 +00:00
SpillPlacement.h Be more conservative when forming compact regions. 2011-08-03 23:09:38 +00:00
Spiller.cpp Moved LiveRangeEdit.h so that it can be called from other parts of the backend, not just libCodeGen 2012-04-02 22:44:18 +00:00
Spiller.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SplitKit.cpp Release build: guard dump functions with 2012-09-11 22:23:19 +00:00
SplitKit.h Make SplitAnalysis::UseSlots private. 2012-01-12 17:53:44 +00:00
StackColoring.cpp Disable the protection from escaped allocas in an attempt to find violating passes. This may break the buildbots. I plan to revert it in a few hours. 2012-09-17 10:21:55 +00:00
StackProtector.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
StackSlotColoring.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
StrongPHIElimination.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
TailDuplication.cpp Remove the `hasFnAttr' method from Function. 2012-09-26 21:48:26 +00:00
TargetFrameLoweringImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TargetInstrInfoImpl.cpp TargetSchedModel API. Implement latency lookup, disabled. 2012-09-18 04:03:34 +00:00
TargetLoweringObjectFileImpl.cpp Remove tabs. 2012-07-19 00:04:14 +00:00
TargetOptionsImpl.cpp Move parts of lib/Target that use CodeGen into lib/CodeGen. 2011-12-15 22:58:58 +00:00
TargetSchedule.cpp TargetSchedule: cleanup computeOperandLatency logic & diagnostics. 2012-09-18 18:20:02 +00:00
TwoAddressInstructionPass.cpp Stop adding <imp-def> operands when expanding REG_SEQUENCE. 2012-09-17 23:03:21 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Fix a significant recent(?) regression. StackSlotColoring no longer did anything 2012-09-21 20:04:28 +00:00
VirtRegMap.h Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments. 2012-09-15 17:09:36 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.