forked from OSchip/llvm-project
87 lines
4.0 KiB
TableGen
87 lines
4.0 KiB
TableGen
//===---------------------------*-tablegen-*-------------------------------===//
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//===------------- X86InstrKL.td - KL Instruction Set Extension -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel key locker
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// instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Key Locker instructions
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let SchedRW = [WriteSystem], Predicates = [HasKL] in {
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let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
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def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
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"loadiwkey\t{$src2, $src1|$src1, $src2}",
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[(int_x86_loadiwkey XMM0, VR128:$src1, VR128:$src2, EAX)]>, T8XS,
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NotMemoryFoldable;
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}
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let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
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def ENCODEKEY128 : I<0xFA, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"encodekey128\t{$src, $dst|$dst, $src}", []>, T8XS,
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NotMemoryFoldable;
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}
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let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
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def ENCODEKEY256 : I<0xFB, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"encodekey256\t{$src, $dst|$dst, $src}", []>, T8XS,
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NotMemoryFoldable;
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}
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let Constraints = "$src1 = $dst",
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Defs = [EFLAGS] in {
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def AESENC128KL : I<0xDC, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
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"aesenc128kl\t{$src2, $src1|$src1, $src2}",
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[(set VR128:$dst, EFLAGS,
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(X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
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NotMemoryFoldable;
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def AESDEC128KL : I<0xDD, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
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"aesdec128kl\t{$src2, $src1|$src1, $src2}",
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[(set VR128:$dst, EFLAGS,
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(X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
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NotMemoryFoldable;
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def AESENC256KL : I<0xDE, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
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"aesenc256kl\t{$src2, $src1|$src1, $src2}",
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[(set VR128:$dst, EFLAGS,
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(X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
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NotMemoryFoldable;
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def AESDEC256KL : I<0xDF, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, opaquemem:$src2),
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"aesdec256kl\t{$src2, $src1|$src1, $src2}",
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[(set VR128:$dst, EFLAGS,
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(X86aesdec256kl VR128:$src1, addr:$src2))]>, T8XS,
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NotMemoryFoldable;
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}
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} // SchedRW, Predicates
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let SchedRW = [WriteSystem], Predicates = [HasWIDEKL] in {
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let Uses = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
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Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
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mayLoad = 1 in {
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def AESENCWIDE128KL : I<0xD8, MRM0m, (outs), (ins opaquemem:$src),
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"aesencwide128kl\t$src", []>, T8XS,
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NotMemoryFoldable;
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def AESDECWIDE128KL : I<0xD8, MRM1m, (outs), (ins opaquemem:$src),
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"aesdecwide128kl\t$src", []>, T8XS,
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NotMemoryFoldable;
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def AESENCWIDE256KL : I<0xD8, MRM2m, (outs), (ins opaquemem:$src),
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"aesencwide256kl\t$src", []>, T8XS,
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NotMemoryFoldable;
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def AESDECWIDE256KL : I<0xD8, MRM3m, (outs), (ins opaquemem:$src),
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"aesdecwide256kl\t$src", []>, T8XS,
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NotMemoryFoldable;
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}
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} // SchedRW, Predicates
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