forked from OSchip/llvm-project
82 lines
2.5 KiB
ArmAsm
82 lines
2.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid result register
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sqincb w0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb w0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb wsp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb wsp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb sp
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb sp
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Operands not matching up
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sqincb x0, w1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register
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// CHECK-NEXT: sqincb x0, w1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, x0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb x0, x0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Immediate not compatible with encode/decode function.
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sqincb x0, all, mul #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincb x0, all, mul #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, all, mul #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincb x0, all, mul #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, all, mul #17
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
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// CHECK-NEXT: sqincb x0, all, mul #17
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid predicate patterns
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sqincb x0, vl512
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb x0, vl512
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, vl9
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sqincb x0, vl9
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, #-1
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqincb x0, #-1
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sqincb x0, #32
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern
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// CHECK-NEXT: sqincb x0, #32
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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