forked from OSchip/llvm-project
147 lines
5.4 KiB
ArmAsm
147 lines
5.4 KiB
ArmAsm
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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ldff1h { z31.h }, p7/z, [sp]
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// CHECK-INST: ldff1h { z31.h }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f bf a4 <unknown>
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ldff1h { z31.s }, p7/z, [sp]
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// CHECK-INST: ldff1h { z31.s }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f df a4 <unknown>
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ldff1h { z31.d }, p7/z, [sp]
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// CHECK-INST: ldff1h { z31.d }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xff,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f ff a4 <unknown>
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ldff1h { z31.h }, p7/z, [sp, xzr, lsl #1]
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// CHECK-INST: ldff1h { z31.h }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f bf a4 <unknown>
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ldff1h { z31.s }, p7/z, [sp, xzr, lsl #1]
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// CHECK-INST: ldff1h { z31.s }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f df a4 <unknown>
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ldff1h { z31.d }, p7/z, [sp, xzr, lsl #1]
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// CHECK-INST: ldff1h { z31.d }, p7/z, [sp]
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// CHECK-ENCODING: [0xff,0x7f,0xff,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f ff a4 <unknown>
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ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
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// CHECK-INST: ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]
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// CHECK-ENCODING: [0x00,0x60,0xa0,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 a0 a4 <unknown>
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ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]
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// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]
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// CHECK-ENCODING: [0x00,0x60,0xc0,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 c0 a4 <unknown>
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ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
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// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]
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// CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
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ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
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// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]
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// CHECK-ENCODING: [0x00,0x60,0x80,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 80 84 <unknown>
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ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
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// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]
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// CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 c0 84 <unknown>
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ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
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// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]
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// CHECK-ENCODING: [0xff,0x7f,0xbf,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f bf 84 <unknown>
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ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
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// CHECK-INST: ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]
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// CHECK-ENCODING: [0xff,0x7f,0xff,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff 7f ff 84 <unknown>
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ldff1h { z31.d }, p7/z, [sp, z31.d]
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// CHECK-INST: ldff1h { z31.d }, p7/z, [sp, z31.d]
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// CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff ff df c4 <unknown>
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ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
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// CHECK-INST: ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]
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// CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
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ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
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// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]
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// CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
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ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
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// CHECK-INST: ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]
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// CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>
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ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
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// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]
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// CHECK-ENCODING: [0x00,0x60,0xa0,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 a0 c4 <unknown>
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ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
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// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]
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// CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 e0 c4 <unknown>
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ldff1h { z31.s }, p7/z, [z31.s, #62]
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// CHECK-INST: ldff1h { z31.s }, p7/z, [z31.s, #62]
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// CHECK-ENCODING: [0xff,0xff,0xbf,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff ff bf 84 <unknown>
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ldff1h { z0.s }, p0/z, [z0.s]
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// CHECK-INST: ldff1h { z0.s }, p0/z, [z0.s]
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// CHECK-ENCODING: [0x00,0xe0,0xa0,0x84]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 e0 a0 84 <unknown>
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ldff1h { z31.d }, p7/z, [z31.d, #62]
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// CHECK-INST: ldff1h { z31.d }, p7/z, [z31.d, #62]
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// CHECK-ENCODING: [0xff,0xff,0xbf,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: ff ff bf c4 <unknown>
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ldff1h { z0.d }, p0/z, [z0.d]
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// CHECK-INST: ldff1h { z0.d }, p0/z, [z0.d]
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// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 e0 a0 c4 <unknown>
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