forked from OSchip/llvm-project
83 lines
3.0 KiB
ArmAsm
83 lines
3.0 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// Invalid predicate
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fmla z0.h, p8/m, z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: fmla z0.h, p8/m, z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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fmla z0.s, p7/m, z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmla z0.s, p7/m, z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// z register out of range for index
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fmla z0.h, z1.h, z8.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z7.h
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// CHECK-NEXT: fmla z0.h, z1.h, z8.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.s, z1.s, z8.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.s..z7.s
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// CHECK-NEXT: fmla z0.s, z1.s, z8.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.d, z1.d, z16.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
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// CHECK-NEXT: fmla z0.d, z1.d, z16.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element index
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fmla z0.h, z1.h, z2.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmla z0.h, z1.h, z2.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.h, z1.h, z2.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmla z0.h, z1.h, z2.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.s, z1.s, z2.s[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: fmla z0.s, z1.s, z2.s[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.s, z1.s, z2.s[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: fmla z0.s, z1.s, z2.s[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.d, z1.d, z2.d[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: fmla z0.d, z1.d, z2.d[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmla z0.d, z1.d, z2.d[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
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// CHECK-NEXT: fmla z0.d, z1.d, z2.d[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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fmla z0.d, z1.d, z7.d[1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: fmla z0.d, z1.d, z7.d[1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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