forked from OSchip/llvm-project
38 lines
1.4 KiB
ArmAsm
38 lines
1.4 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Source and Destination Registers must match
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fcadd z0.d, p2/m, z1.d, z2.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
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// CHECK-NEXT: fcadd z0.d, p2/m, z1.d, z2.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Restricted predicate out of range.
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fcadd z0.d, p8/m, z0.d, z1.d, #90
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: fcadd z0.d, p8/m, z0.d, z1.d, #90
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid rotation
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fcadd z0.d, p0/m, z0.d, z1.d, #0
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #0
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcadd z0.d, p0/m, z0.d, z1.d, #180
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #180
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcadd z0.d, p0/m, z0.d, z1.d, #450
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
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// CHECK-NEXT: fcadd z0.d, p0/m, z0.d, z1.d, #450
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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