forked from OSchip/llvm-project
31 lines
837 B
LLVM
31 lines
837 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck -check-prefix=RV32I %s
|
|
|
|
; Ensure that the ISDOpcodes ADDC, ADDE, SUBC, SUBE are handled correctly
|
|
|
|
define i64 @addc_adde(i64 %a, i64 %b) {
|
|
; RV32I-LABEL: addc_adde:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: add a1, a1, a3
|
|
; RV32I-NEXT: add a2, a0, a2
|
|
; RV32I-NEXT: sltu a0, a2, a0
|
|
; RV32I-NEXT: add a1, a1, a0
|
|
; RV32I-NEXT: mv a0, a2
|
|
; RV32I-NEXT: ret
|
|
%1 = add i64 %a, %b
|
|
ret i64 %1
|
|
}
|
|
|
|
define i64 @subc_sube(i64 %a, i64 %b) {
|
|
; RV32I-LABEL: subc_sube:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: sub a1, a1, a3
|
|
; RV32I-NEXT: sltu a3, a0, a2
|
|
; RV32I-NEXT: sub a1, a1, a3
|
|
; RV32I-NEXT: sub a0, a0, a2
|
|
; RV32I-NEXT: ret
|
|
%1 = sub i64 %a, %b
|
|
ret i64 %1
|
|
}
|