forked from OSchip/llvm-project
166 lines
4.3 KiB
YAML
166 lines
4.3 KiB
YAML
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define void @test_s8() { ret void }
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define void @test_s16() { ret void }
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define void @test_s32() { ret void }
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define void @test_gep() { ret void }
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define void @test_load_from_stack() { ret void }
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...
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---
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name: test_s8
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# CHECK-LABEL: name: test_s8
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
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%1(s8) = G_LOAD %0(p0) :: (load 1)
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; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1)
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G_STORE %1(s8), %0(p0) :: (store 1)
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; CHECK: t2STRBi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 1)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_s16
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# CHECK-LABEL: name: test_s16
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
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%1(s16) = G_LOAD %0(p0) :: (load 2)
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; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRHi12 %[[P]], 0, 14, $noreg :: (load 2)
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G_STORE %1(s16), %0(p0) :: (store 2)
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; CHECK: t2STRHi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 2)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_s32
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# CHECK-LABEL: name: test_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0
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%1(s32) = G_LOAD %0(p0) :: (load 4)
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; CHECK: %[[V:[0-9]+]]:gpr = t2LDRi12 %[[P]], 0, 14, $noreg :: (load 4)
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G_STORE %1(s32), %0(p0) :: (store 4)
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; CHECK: t2STRi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 4)
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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---
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name: test_gep
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# CHECK-LABEL: name: test_gep
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1
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%2(p0) = G_GEP %0, %1(s32)
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; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg
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$r0 = COPY %2(p0)
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; CHECK: $r0 = COPY [[GEP]]
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BX_RET 14, $noreg, implicit $r0
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; CHECK: BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_load_from_stack
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# CHECK-LABEL: name: test_load_from_stack
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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- { id: 3, class: gprb }
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- { id: 4, class: gprb }
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fixedStack:
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- { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1
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# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8
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body: |
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bb.0:
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liveins: $r0, $r1, $r2, $r3
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%0(p0) = G_FRAME_INDEX %fixed-stack.2
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; CHECK: [[FI32VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg
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%1(s32) = G_LOAD %0(p0) :: (load 4)
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; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg
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$r0 = COPY %1
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; CHECK: $r0 = COPY [[LD32VREG]]
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%2(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[FI1VREG:%[0-9]+]]:gprnopc = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg
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%3(s1) = G_LOAD %2(p0) :: (load 1)
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; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg
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%4(s32) = G_ANYEXT %3(s1)
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; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]]
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$r0 = COPY %4
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; CHECK: $r0 = COPY [[RES]]
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BX_RET 14, $noreg
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; CHECK: BX_RET 14, $noreg
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...
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