llvm-project/llvm/test/CodeGen
Piotr Sobczak 3abef8f9ea [AMDGPU] Change section name with metadata access
Summary:
The commit rL348922 introduced a means to set Metadata
section kind for a global variable, if its explicit section
name was prefixed with ".AMDGPU.metadata.".

This patch changes that prefix to ".AMDGPU.comment.",
as "metadata" in the section name might lead to
ambiguity with metadata used by AMD PAL runtime.

Change-Id: Idd4748800d6fe801441d91595fc21e5a4171e668

Reviewers: kzhuravl

Reviewed By: kzhuravl

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D56197

llvm-svn: 350292
2019-01-03 11:22:58 +00:00
..
AArch64 Reversing the commit in revision 350186. Revision causes regression in 4 2019-01-01 07:28:55 +00:00
AMDGPU [AMDGPU] Change section name with metadata access 2019-01-03 11:22:58 +00:00
ARC
ARM [ARM] Set Defs = [CPSR] for COPY_STRUCT_BYVAL, as it clobbers CPSR. 2018-12-21 18:07:10 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF [BPF] Generate BTF DebugInfo under BPF target 2018-12-19 16:40:25 +00:00
Generic Move llc-start-stop-instance to x86 2018-12-04 18:19:08 +00:00
Hexagon [DAGCombiner] allow narrowing of add followed by truncate 2018-12-22 17:10:31 +00:00
Inputs
Lanai [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00
MIR [Dwarf/AArch64] Return address signing B key dwarf support 2018-12-21 10:45:08 +00:00
MSP430 [MSP430] Optimize srl/sra in case of A >> (8 + N) 2018-11-19 10:43:02 +00:00
Mips [MIPS GlobalISel] Select G_SELECT 2018-12-25 14:42:30 +00:00
NVPTX [NVPTX] Allow libcalls that are defined in the current module. 2018-12-26 19:12:31 +00:00
Nios2
PowerPC [Power9] Enable the Out-of-Order scheduling model for P9 hw 2019-01-03 05:04:18 +00:00
RISCV [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
SPARC [Sparc] Use float register for integer constrained with "f" in inline asm 2018-12-13 15:13:29 +00:00
SystemZ [SystemZ] Make better use of VLLEZ 2018-12-20 13:05:03 +00:00
Thumb [ARM] Complete the Thumb1 shift+and->shift+shift transforms. 2018-12-20 23:39:54 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly][NFC] Elaborate on simd-noopt test comment 2019-01-02 20:43:08 +00:00
WinCFGuard
WinEH
X86 [CodeGen] Skip over dbg-instr in twoaddr pass 2019-01-03 08:36:06 +00:00
XCore [Targets] Add errors for tiny and kernel codemodel on targets that don't support them 2018-12-07 12:10:23 +00:00