forked from OSchip/llvm-project
38 lines
1.8 KiB
LLVM
38 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -stop-after=irtranslator -global-isel %s -o - | FileCheck %s
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; Check that we correctly skip over disabled inputs
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define amdgpu_ps void @disabled_input(float inreg %arg0, float %psinput0, float %psinput1) #1 {
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; CHECK-LABEL: name: disabled_input
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; CHECK: bb.1.main_body:
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; CHECK: liveins: $sgpr2, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
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; CHECK: S_ENDPGM 0
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main_body:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
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ret void
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}
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define amdgpu_ps void @disabled_input_struct(float inreg %arg0, { float, float } %psinput0, float %psinput1) #1 {
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; CHECK-LABEL: name: disabled_input_struct
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; CHECK: bb.1.main_body:
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; CHECK: liveins: $sgpr2, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), 0, 15, [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY1]](s32), 0, 0
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; CHECK: S_ENDPGM 0
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main_body:
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg0, float %arg0, float %arg0, float %psinput1, i1 false, i1 false) #0
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg) #0
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attributes #0 = { nounwind }
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attributes #1 = { "InitialPSInputAddr"="0x00002" }
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