forked from OSchip/llvm-project
110 lines
4.4 KiB
LLVM
110 lines
4.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx600 -verify-machineinstrs <%s | FileCheck -enable-var-scope -check-prefixes=GCN,SICI,SI %s
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx700 -verify-machineinstrs <%s | FileCheck -enable-var-scope -check-prefixes=GCN,SICI,CI %s
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; Check that an addrspace(1) (const) load with various combinations of
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; uniform, nonuniform and constant address components all load with an
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; addr64 mubuf with no readfirstlane.
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@indexable = internal unnamed_addr addrspace(1) constant [6 x <3 x float>] [<3 x float> <float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 0.000000e+00>, <3 x float> <float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 0.000000e+00, float 1.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 0.000000e+00, float 1.000000e+00>, <3 x float> <float 1.000000e+00, float 1.000000e+00, float 0.000000e+00>]
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; GCN-LABEL: {{^}}nonuniform_uniform:
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; GCN-NOT: readfirstlane
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; SI: buffer_load_dwordx4 {{.*}} addr64
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; CI: buffer_load_dwordx3 {{.*}} addr64
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define amdgpu_ps float @nonuniform_uniform(i32 %arg18) {
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.entry:
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%tmp31 = sext i32 %arg18 to i64
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* @indexable, i64 0, i64 %tmp31
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%tmp33 = load <3 x float>, <3 x float> addrspace(1)* %tmp32, align 16
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%tmp34 = extractelement <3 x float> %tmp33, i32 0
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ret float %tmp34
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}
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; GCN-LABEL: {{^}}uniform_nonuniform:
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; GCN-NOT: readfirstlane
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; SI: buffer_load_dwordx4 {{.*}} addr64
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; CI: buffer_load_dwordx3 {{.*}} addr64
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define amdgpu_ps float @uniform_nonuniform(i32 inreg %offset, i32 %arg18) {
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.entry:
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%tmp1 = zext i32 %arg18 to i64
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%tmp2 = inttoptr i64 %tmp1 to [6 x <3 x float>] addrspace(1)*
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* %tmp2, i32 0, i32 %offset
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%tmp33 = load <3 x float>, <3 x float> addrspace(1)* %tmp32, align 16
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%tmp34 = extractelement <3 x float> %tmp33, i32 0
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ret float %tmp34
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}
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; GCN-LABEL: {{^}}const_nonuniform:
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; GCN-NOT: readfirstlane
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; SI: buffer_load_dwordx4 {{.*}} addr64
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; CI: buffer_load_dwordx3 {{.*}} addr64
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define amdgpu_ps float @const_nonuniform(i32 %arg18) {
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.entry:
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%tmp1 = zext i32 %arg18 to i64
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%tmp2 = inttoptr i64 %tmp1 to [6 x <3 x float>] addrspace(1)*
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* %tmp2, i32 0, i32 1
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%tmp33 = load <3 x float>, <3 x float> addrspace(1)* %tmp32, align 16
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%tmp34 = extractelement <3 x float> %tmp33, i32 0
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ret float %tmp34
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}
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; GCN-LABEL: {{^}}nonuniform_nonuniform:
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; GCN-NOT: readfirstlane
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; SI: buffer_load_dwordx4 {{.*}} addr64
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; CI: buffer_load_dwordx3 {{.*}} addr64
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define amdgpu_ps float @nonuniform_nonuniform(i32 %offset, i32 %arg18) {
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.entry:
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%tmp1 = zext i32 %arg18 to i64
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%tmp2 = inttoptr i64 %tmp1 to [6 x <3 x float>] addrspace(1)*
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* %tmp2, i32 0, i32 %offset
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%tmp33 = load <3 x float>, <3 x float> addrspace(1)* %tmp32, align 16
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%tmp34 = extractelement <3 x float> %tmp33, i32 0
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ret float %tmp34
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}
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; GCN-LABEL: {{^}}nonuniform_uniform_const:
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; GCN-NOT: readfirstlane
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; SICI: buffer_load_dword {{.*}} addr64
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define amdgpu_ps float @nonuniform_uniform_const(i32 %arg18) {
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.entry:
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%tmp31 = sext i32 %arg18 to i64
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* @indexable, i64 0, i64 %tmp31, i64 1
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%tmp33 = load float, float addrspace(1)* %tmp32, align 4
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ret float %tmp33
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}
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; GCN-LABEL: {{^}}uniform_nonuniform_const:
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; GCN-NOT: readfirstlane
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; SICI: buffer_load_dword {{.*}} addr64
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define amdgpu_ps float @uniform_nonuniform_const(i32 inreg %offset, i32 %arg18) {
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.entry:
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%tmp1 = zext i32 %arg18 to i64
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%tmp2 = inttoptr i64 %tmp1 to [6 x <3 x float>] addrspace(1)*
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* %tmp2, i32 0, i32 %offset, i32 1
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%tmp33 = load float, float addrspace(1)* %tmp32, align 4
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ret float %tmp33
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}
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; GCN-LABEL: {{^}}nonuniform_nonuniform_const:
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; GCN-NOT: readfirstlane
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; SICI: buffer_load_dword {{.*}} addr64
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define amdgpu_ps float @nonuniform_nonuniform_const(i32 %offset, i32 %arg18) {
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.entry:
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%tmp1 = zext i32 %arg18 to i64
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%tmp2 = inttoptr i64 %tmp1 to [6 x <3 x float>] addrspace(1)*
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%tmp32 = getelementptr [6 x <3 x float>], [6 x <3 x float>] addrspace(1)* %tmp2, i32 0, i32 %offset, i32 1
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%tmp33 = load float, float addrspace(1)* %tmp32, align 4
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ret float %tmp33
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}
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