forked from OSchip/llvm-project
240 lines
13 KiB
YAML
240 lines
13 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=COMMON,ADDR64
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# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=COMMON,NO-ADDR64
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# Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
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#
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# On ADDR64 hardware we optimize the _ADDR64 and _OFFSET cases to avoid
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# needing a waterfall. For all other instruction variants, and when we are
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# on non-ADDR64 hardware, we emit a waterfall loop.
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# COMMON-LABEL: name: idxen
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# COMMON-LABEL: bb.0:
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# COMMON-NEXT: successors: %bb.1({{.*}})
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# COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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# COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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# COMMON-LABEL: bb.1:
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# COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
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# COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
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# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
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# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
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# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
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# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
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# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
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# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
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# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
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# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
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# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec
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# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
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# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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# COMMON-LABEL bb.2:
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# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
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---
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name: idxen
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$vgpr1', virtual-reg: '%1' }
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- { reg: '$vgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr3', virtual-reg: '%3' }
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- { reg: '$vgpr4', virtual-reg: '%4' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
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%5:sreg_64 = COPY $sgpr30_sgpr31
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%4:vgpr_32 = COPY $vgpr4
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%3:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$vgpr0 = COPY %7
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
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...
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# COMMON-LABEL: name: offen
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# COMMON-LABEL: bb.0:
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# COMMON-NEXT: successors: %bb.1({{.*}})
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# COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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# COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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# COMMON-LABEL: bb.1:
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# COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
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# COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
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# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
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# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
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# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
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# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
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# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
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# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
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# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
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# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
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# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec
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# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
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# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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# COMMON-LABEL bb.2:
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# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
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---
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name: offen
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$vgpr1', virtual-reg: '%1' }
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- { reg: '$vgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr3', virtual-reg: '%3' }
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- { reg: '$vgpr4', virtual-reg: '%4' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
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%5:sreg_64 = COPY $sgpr30_sgpr31
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%4:vgpr_32 = COPY $vgpr4
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%3:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$vgpr0 = COPY %7
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
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...
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# COMMON-LABEL: name: bothen
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# COMMON-LABEL: bb.0:
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# COMMON-NEXT: successors: %bb.1({{.*}})
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# COMMON: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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# COMMON: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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# COMMON-LABEL: bb.1:
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# COMMON-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
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# COMMON: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
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# COMMON: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
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# COMMON: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
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# COMMON: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
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# COMMON: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
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# COMMON: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
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# COMMON: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
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# COMMON: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
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# COMMON: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
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# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec
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# COMMON: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
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# COMMON: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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# COMMON-LABEL bb.2:
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# COMMON: $exec = S_MOV_B64 [[SAVEEXEC]]
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---
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name: bothen
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$vgpr1', virtual-reg: '%1' }
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- { reg: '$vgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr3', virtual-reg: '%3' }
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- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
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%5:sreg_64 = COPY $sgpr30_sgpr31
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%4:vreg_64 = COPY $vgpr4_vgpr5
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%3:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_BOTHEN %4, killed %6, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$vgpr0 = COPY %7
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
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...
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# COMMON-LABEL: name: addr64
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# COMMON-LABEL: bb.0:
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# COMMON: %12:vreg_64 = COPY %8.sub0_sub1
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# COMMON: %13:sreg_64 = S_MOV_B64 0
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# COMMON: %14:sgpr_32 = S_MOV_B32 0
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# COMMON: %15:sgpr_32 = S_MOV_B32 61440
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# COMMON: %16:sreg_128 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2, %15, %subreg.sub3
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# COMMON: %9:vgpr_32 = V_ADD_I32_e32 %12.sub0, %4.sub0, implicit-def $vcc, implicit $exec
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# COMMON: %10:vgpr_32 = V_ADDC_U32_e32 %12.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
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# COMMON: %11:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %10, %subreg.sub1
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# COMMON: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %11, killed %16, 0, 0, 0, 0, 0, implicit $exec
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---
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name: addr64
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$vgpr1', virtual-reg: '%1' }
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- { reg: '$vgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr3', virtual-reg: '%3' }
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- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
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%5:sreg_64 = COPY $sgpr30_sgpr31
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%4:vreg_64 = COPY $vgpr4_vgpr5
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%3:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 %4, killed %6, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$vgpr0 = COPY %7
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
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...
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# COMMON-LABEL: name: offset
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# COMMON-LABEL: bb.0:
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# NO-ADDR64-NEXT: successors: %bb.1({{.*}})
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# NO-ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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# NO-ADDR64: [[SAVEEXEC:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec
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# NO-ADDR64-LABEL: bb.1:
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# NO-ADDR64-NEXT: successors: %bb.1({{.*}}), %bb.2({{.*}})
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# NO-ADDR64: [[SRSRC0:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub0, implicit $exec
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# NO-ADDR64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
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# NO-ADDR64: [[SRSRC2:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub2, implicit $exec
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# NO-ADDR64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
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# NO-ADDR64: [[SRSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1, [[SRSRC2]], %subreg.sub2, [[SRSRC3]], %subreg.sub3
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# NO-ADDR64: [[CMP0:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub0_sub1, [[VRSRC]].sub0_sub1, implicit $exec
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# NO-ADDR64: [[CMP1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U64_e64 [[SRSRC]].sub2_sub3, [[VRSRC]].sub2_sub3, implicit $exec
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# NO-ADDR64: [[CMP:%[0-9]+]]:sreg_64 = S_AND_B64 [[CMP0]], [[CMP1]], implicit-def $scc
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# NO-ADDR64: [[TMPEXEC:%[0-9]+]]:sreg_64 = S_AND_SAVEEXEC_B64 killed [[CMP]], implicit-def $exec, implicit-def $scc, implicit $exec
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# NO-ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed [[SRSRC]], 0, 0, 0, 0, 0, implicit $exec
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# NO-ADDR64: $exec = S_XOR_B64_term $exec, [[TMPEXEC]], implicit-def $scc
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# NO-ADDR64: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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# NO-ADDR64-LABEL bb.2:
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# NO-ADDR64: $exec = S_MOV_B64 [[SAVEEXEC]]
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# ADDR64: [[VRSRC:%[0-9]+]]:vreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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# ADDR64: [[RSRCPTR:%[0-9]+]]:vreg_64 = COPY [[VRSRC]].sub0_sub1
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# ADDR64: [[ZERO64:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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# ADDR64: [[RSRCFMTLO:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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# ADDR64: [[RSRCFMTHI:%[0-9]+]]:sgpr_32 = S_MOV_B32 61440
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# ADDR64: [[ZERORSRC:%[0-9]+]]:sreg_128 = REG_SEQUENCE [[ZERO64]], %subreg.sub0_sub1, [[RSRCFMTLO]], %subreg.sub2, [[RSRCFMTHI]], %subreg.sub3
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# ADDR64: [[VADDR64:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[RSRCPTR]].sub0, %subreg.sub0, [[RSRCPTR]].sub1, %subreg.sub1
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# ADDR64: {{[0-9]+}}:vgpr_32 = BUFFER_LOAD_FORMAT_X_ADDR64 [[VADDR64]], [[ZERORSRC]], 0, 0, 0, 0, 0, implicit $exec
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---
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name: offset
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$vgpr1', virtual-reg: '%1' }
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- { reg: '$vgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr3', virtual-reg: '%3' }
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- { reg: '$vgpr4_vgpr5', virtual-reg: '%4' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr30_sgpr31
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%5:sreg_64 = COPY $sgpr30_sgpr31
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%4:vreg_64 = COPY $vgpr4_vgpr5
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%3:vgpr_32 = COPY $vgpr3
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%2:vgpr_32 = COPY $vgpr2
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%1:vgpr_32 = COPY $vgpr1
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%0:vgpr_32 = COPY $vgpr0
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%6:sreg_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%7:vgpr_32 = BUFFER_LOAD_FORMAT_X_OFFSET killed %6, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$vgpr0 = COPY %7
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
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...
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