forked from OSchip/llvm-project
113 lines
3.5 KiB
LLVM
113 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs | FileCheck -check-prefix=VI %s
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;RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefix=GFX9 %s
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; ===================================================================================
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; V_AND_OR_B32
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; ===================================================================================
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define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) {
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; VI-LABEL: and_or:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, v0, v1
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; VI-NEXT: v_or_b32_e32 v0, v0, v2
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_and_or_b32 v0, v0, v1, v2
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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; ThreeOp instruction variant not used due to Constant Bus Limitations
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define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {
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; VI-LABEL: and_or_vgpr_b:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, s2, v0
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; VI-NEXT: v_or_b32_e32 v0, s3, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or_vgpr_b:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_and_b32_e32 v0, s2, v0
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; GFX9-NEXT: v_or_b32_e32 v0, s3, v0
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) {
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; VI-LABEL: and_or_vgpr_ab:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, v0, v1
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; VI-NEXT: v_or_b32_e32 v0, s2, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or_vgpr_ab:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_and_or_b32 v0, v0, v1, s2
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 %a, %b
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%result = or i32 %x, %c
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) {
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; VI-LABEL: and_or_vgpr_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, 4, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or_vgpr_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_and_or_b32 v0, v0, 4, v1
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 4, %a
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%result = or i32 %x, %b
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) {
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; VI-LABEL: and_or_vgpr_const_inline_const:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, 20, v0
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; VI-NEXT: v_or_b32_e32 v0, 0x808, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or_vgpr_const_inline_const:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v1, 0x808
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; GFX9-NEXT: v_and_or_b32 v0, v0, 20, v1
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 20, %a
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%result = or i32 %x, 2056
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) {
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; VI-LABEL: and_or_vgpr_inline_const_x2:
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; VI: ; %bb.0:
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; VI-NEXT: v_and_b32_e32 v0, 4, v0
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; VI-NEXT: v_or_b32_e32 v0, 1, v0
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; VI-NEXT: ; return to shader part epilog
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;
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; GFX9-LABEL: and_or_vgpr_inline_const_x2:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_and_or_b32 v0, v0, 4, 1
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; GFX9-NEXT: ; return to shader part epilog
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%x = and i32 4, %a
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%result = or i32 %x, 1
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%bc = bitcast i32 %result to float
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ret float %bc
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}
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