forked from OSchip/llvm-project
1891 lines
66 KiB
YAML
1891 lines
66 KiB
YAML
# RUN: llc -mtriple arm-linux-gnueabihf -mattr=+vfp2 -float-abi=hard -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix HARD
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# RUN: llc -mtriple arm-linux-gnueabi -mattr=+vfp2,+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-AEABI
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# RUN: llc -mtriple arm-linux-gnu -mattr=+soft-float -float-abi=soft -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefix CHECK -check-prefix SOFT -check-prefix SOFT-DEFAULT
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--- |
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define void @test_frem_float() { ret void }
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define void @test_frem_double() { ret void }
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define void @test_fpow_float() { ret void }
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define void @test_fpow_double() { ret void }
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define void @test_fadd_float() { ret void }
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define void @test_fadd_double() { ret void }
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define void @test_fcmp_true_s32() { ret void }
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define void @test_fcmp_false_s32() { ret void }
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define void @test_fcmp_oeq_s32() { ret void }
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define void @test_fcmp_ogt_s32() { ret void }
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define void @test_fcmp_oge_s32() { ret void }
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define void @test_fcmp_olt_s32() { ret void }
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define void @test_fcmp_ole_s32() { ret void }
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define void @test_fcmp_ord_s32() { ret void }
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define void @test_fcmp_ugt_s32() { ret void }
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define void @test_fcmp_uge_s32() { ret void }
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define void @test_fcmp_ult_s32() { ret void }
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define void @test_fcmp_ule_s32() { ret void }
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define void @test_fcmp_une_s32() { ret void }
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define void @test_fcmp_uno_s32() { ret void }
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define void @test_fcmp_one_s32() { ret void }
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define void @test_fcmp_ueq_s32() { ret void }
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define void @test_fcmp_true_s64() { ret void }
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define void @test_fcmp_false_s64() { ret void }
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define void @test_fcmp_oeq_s64() { ret void }
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define void @test_fcmp_ogt_s64() { ret void }
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define void @test_fcmp_oge_s64() { ret void }
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define void @test_fcmp_olt_s64() { ret void }
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define void @test_fcmp_ole_s64() { ret void }
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define void @test_fcmp_ord_s64() { ret void }
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define void @test_fcmp_ugt_s64() { ret void }
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define void @test_fcmp_uge_s64() { ret void }
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define void @test_fcmp_ult_s64() { ret void }
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define void @test_fcmp_ule_s64() { ret void }
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define void @test_fcmp_une_s64() { ret void }
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define void @test_fcmp_uno_s64() { ret void }
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define void @test_fcmp_one_s64() { ret void }
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define void @test_fcmp_ueq_s64() { ret void }
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...
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---
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name: test_frem_float
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# CHECK-LABEL: name: test_frem_float
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; CHECK-NOT: G_FREM
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; CHECK: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; HARD-DAG: %s0 = COPY [[X]]
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; HARD-DAG: %s1 = COPY [[Y]]
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; SOFT: BLX $fmodf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; HARD: BLX $fmodf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
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; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
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; HARD: [[R:%[0-9]+]](s32) = COPY %s0
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; CHECK: ADJCALLSTACKUP
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; CHECK-NOT: G_FREM
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%2(s32) = G_FREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_frem_double
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# CHECK-LABEL: name: test_frem_double
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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; The inputs may be in the wrong order (depending on the target's
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; endianness), but that's orthogonal to what we're trying to test here.
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; For soft float, we only need to check that the first value, received
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; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
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; through R2-R3, ends up in R2-R3 or R3-R2, when passed to fmod.
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; For hard float, the values need to end up in D0 and D1.
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; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
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; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
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; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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%3(s32) = COPY %r3
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; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
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; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
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%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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; CHECK-NOT: G_FREM
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; CHECK: ADJCALLSTACKDOWN
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
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; HARD-DAG: %d0 = COPY [[X]]
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; HARD-DAG: %d1 = COPY [[Y]]
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; SOFT: BLX $fmod, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; HARD: BLX $fmod, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
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; CHECK: ADJCALLSTACKUP
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; CHECK-NOT: G_FREM
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%6(s64) = G_FREM %4, %5
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%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
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%r0 = COPY %7(s32)
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%r1 = COPY %8(s32)
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BX_RET 14, _, implicit %r0, implicit %r1
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...
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---
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name: test_fpow_float
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# CHECK-LABEL: name: test_fpow_float
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; CHECK-NOT: G_FPOW
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; CHECK: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; HARD-DAG: %s0 = COPY [[X]]
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; HARD-DAG: %s1 = COPY [[Y]]
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; SOFT: BLX $powf, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; HARD: BLX $powf, {{.*}}, implicit %s0, implicit %s1, implicit-def %s0
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; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
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; HARD: [[R:%[0-9]+]](s32) = COPY %s0
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; CHECK: ADJCALLSTACKUP
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; CHECK-NOT: G_FPOW
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%2(s32) = G_FPOW %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fpow_double
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# CHECK-LABEL: name: test_fpow_double
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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; The inputs may be in the wrong order (depending on the target's
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; endianness), but that's orthogonal to what we're trying to test here.
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; For soft float, we only need to check that the first value, received
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; through R0-R1, ends up in R0-R1 or R1-R0, and the second value, received
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; through R2-R3, ends up in R2-R3 or R3-R2, when passed to pow.
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; For hard float, the values need to end up in D0 and D1.
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; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
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; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
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; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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%3(s32) = COPY %r3
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; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
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; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
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%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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; CHECK-NOT: G_FPOW
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; CHECK: ADJCALLSTACKDOWN
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
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; HARD-DAG: %d0 = COPY [[X]]
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; HARD-DAG: %d1 = COPY [[Y]]
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; SOFT: BLX $pow, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; HARD: BLX $pow, {{.*}}, implicit %d0, implicit %d1, implicit-def %d0
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; CHECK: ADJCALLSTACKUP
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; CHECK-NOT: G_FPOW
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%6(s64) = G_FPOW %4, %5
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%7(s32), %8(s32) = G_UNMERGE_VALUES %6(s64)
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%r0 = COPY %7(s32)
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%r1 = COPY %8(s32)
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BX_RET 14, _, implicit %r0, implicit %r1
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...
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---
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name: test_fadd_float
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# CHECK-LABEL: name: test_fadd_float
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; HARD: [[R:%[0-9]+]](s32) = G_FADD [[X]], [[Y]]
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; SOFT-NOT: G_FADD
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; SOFT-AEABI: BLX $__aeabi_fadd, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: BLX $__addsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_FADD
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%2(s32) = G_FADD %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fadd_double
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# CHECK-LABEL: name: test_fadd_double
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
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; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
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; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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%3(s32) = COPY %r3
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; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]]
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; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]]
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%4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
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; HARD: [[R:%[0-9]+]](s64) = G_FADD [[X]], [[Y]]
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; SOFT-NOT: G_FADD
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
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; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
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; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
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; SOFT-AEABI: BLX $__aeabi_dadd, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; SOFT-DEFAULT: BLX $__adddf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_FADD
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%6(s64) = G_FADD %4, %5
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; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
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%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
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%r0 = COPY %7(s32)
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%r1 = COPY %8(s32)
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BX_RET 14, _, implicit %r0, implicit %r1
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...
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---
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name: test_fcmp_true_s32
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# CHECK-LABEL: name: test_fcmp_true_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%2(s1) = G_FCMP floatpred(true), %0(s32), %1
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; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
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; SOFT-NOT: G_FCMP
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; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
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; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
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; SOFT-NOT: G_FCMP
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%3(s32) = G_ZEXT %2(s1)
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; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
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%r0 = COPY %3(s32)
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; CHECK: %r0 = COPY [[REXT]]
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_false_s32
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# CHECK-LABEL: name: test_fcmp_false_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_oeq_s32
|
|
# CHECK-LABEL: name: test_fcmp_oeq_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ogt_s32
|
|
# CHECK-LABEL: name: test_fcmp_ogt_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_oge_s32
|
|
# CHECK-LABEL: name: test_fcmp_oge_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_olt_s32
|
|
# CHECK-LABEL: name: test_fcmp_olt_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ole_s32
|
|
# CHECK-LABEL: name: test_fcmp_ole_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ord_s32
|
|
# CHECK-LABEL: name: test_fcmp_ord_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ord), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ugt_s32
|
|
# CHECK-LABEL: name: test_fcmp_ugt_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ugt), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmple, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_uge_s32
|
|
# CHECK-LABEL: name: test_fcmp_uge_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(uge), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ult_s32
|
|
# CHECK-LABEL: name: test_fcmp_ult_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ult), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpge, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ule_s32
|
|
# CHECK-LABEL: name: test_fcmp_ule_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ule), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_une_s32
|
|
# CHECK-LABEL: name: test_fcmp_une_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(une), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__nesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_uno_s32
|
|
# CHECK-LABEL: name: test_fcmp_uno_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_one_s32
|
|
# CHECK-LABEL: name: test_fcmp_one_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmplt, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
|
|
; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
|
|
; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
|
|
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
|
|
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
|
|
; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ueq_s32
|
|
# CHECK-LABEL: name: test_fcmp_ueq_s32
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
|
|
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X]]
|
|
; SOFT-DAG: %r1 = COPY [[Y]]
|
|
; SOFT-AEABI: BLX $__aeabi_fcmpun, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
|
|
; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
|
|
; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
|
|
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
|
|
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
|
|
; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
|
|
; SOFT-NOT: G_FCMP
|
|
%3(s32) = G_ZEXT %2(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %3(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_true_s64
|
|
# CHECK-LABEL: name: test_fcmp_true_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(true), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 -1
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_false_s64
|
|
# CHECK-LABEL: name: test_fcmp_false_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(false), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: [[REXT:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]](s32)
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_oeq_s64
|
|
# CHECK-LABEL: name: test_fcmp_oeq_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ogt_s64
|
|
# CHECK-LABEL: name: test_fcmp_ogt_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_oge_s64
|
|
# CHECK-LABEL: name: test_fcmp_oge_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(oge), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_olt_s64
|
|
# CHECK-LABEL: name: test_fcmp_olt_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(olt), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ole_s64
|
|
# CHECK-LABEL: name: test_fcmp_ole_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ole), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ord_s64
|
|
# CHECK-LABEL: name: test_fcmp_ord_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ord), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ord), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ugt_s64
|
|
# CHECK-LABEL: name: test_fcmp_ugt_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ugt), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ugt), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmple, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_uge_s64
|
|
# CHECK-LABEL: name: test_fcmp_uge_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(uge), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uge), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ult_s64
|
|
# CHECK-LABEL: name: test_fcmp_ult_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ult), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ult), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpge, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_ule_s64
|
|
# CHECK-LABEL: name: test_fcmp_ule_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(ule), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ule), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_une_s64
|
|
# CHECK-LABEL: name: test_fcmp_une_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(une), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(une), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__nedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_fcmp_uno_s64
|
|
# CHECK-LABEL: name: test_fcmp_uno_s64
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
- { id: 3, class: _ }
|
|
- { id: 4, class: _ }
|
|
- { id: 5, class: _ }
|
|
- { id: 6, class: _ }
|
|
- { id: 7, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1, %r2, %r3
|
|
|
|
%0(s32) = COPY %r0
|
|
%1(s32) = COPY %r1
|
|
%2(s32) = COPY %r2
|
|
%3(s32) = COPY %r3
|
|
; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
|
|
; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
|
|
; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
|
|
; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
|
|
%4(s64) = G_MERGE_VALUES %0(s32), %1
|
|
%5(s64) = G_MERGE_VALUES %2(s32), %3
|
|
; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
|
|
; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
|
|
%6(s1) = G_FCMP floatpred(uno), %4(s64), %5
|
|
; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
|
|
; SOFT-NOT: G_FCMP
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X0]]
|
|
; SOFT-DAG: %r1 = COPY [[X1]]
|
|
; SOFT-DAG: %r2 = COPY [[Y0]]
|
|
; SOFT-DAG: %r3 = COPY [[Y1]]
|
|
; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
|
|
; SOFT: [[RET:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-AEABI: [[R:%[0-9]+]](s1) = G_TRUNC [[RET]](s32)
|
|
; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
|
|
; SOFT-DEFAULT: [[R:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
|
|
; SOFT-NOT: G_FCMP
|
|
%7(s32) = G_ZEXT %6(s1)
|
|
; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
|
|
%r0 = COPY %7(s32)
|
|
; CHECK: %r0 = COPY [[REXT]]
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
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name: test_fcmp_one_s64
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# CHECK-LABEL: name: test_fcmp_one_s64
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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%3(s32) = COPY %r3
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; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
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; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
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; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
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%4(s64) = G_MERGE_VALUES %0(s32), %1
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%5(s64) = G_MERGE_VALUES %2(s32), %3
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; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
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; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
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%6(s1) = G_FCMP floatpred(one), %4(s64), %5
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; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
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; SOFT-NOT: G_FCMP
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X0]]
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; SOFT-DAG: %r1 = COPY [[X1]]
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; SOFT-DAG: %r2 = COPY [[Y0]]
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; SOFT-DAG: %r3 = COPY [[Y1]]
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; SOFT-AEABI: BLX $__aeabi_dcmpgt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT-DEFAULT: BLX $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
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; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(sgt), [[RET1]](s32), [[ZERO]]
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; SOFT-NOT: G_FCMP
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X0]]
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; SOFT-DAG: %r1 = COPY [[X1]]
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; SOFT-DAG: %r2 = COPY [[Y0]]
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; SOFT-DAG: %r3 = COPY [[Y1]]
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; SOFT-AEABI: BLX $__aeabi_dcmplt, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT-DEFAULT: BLX $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
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; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
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; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
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; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
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; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
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; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
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; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
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; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
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; SOFT-NOT: G_FCMP
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%7(s32) = G_ZEXT %6(s1)
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; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
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%r0 = COPY %7(s32)
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; CHECK: %r0 = COPY [[REXT]]
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_fcmp_ueq_s64
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# CHECK-LABEL: name: test_fcmp_ueq_s64
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1, %r2, %r3
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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%2(s32) = COPY %r2
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%3(s32) = COPY %r3
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; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1
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; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2
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; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3
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%4(s64) = G_MERGE_VALUES %0(s32), %1
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%5(s64) = G_MERGE_VALUES %2(s32), %3
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; HARD-DAG: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32)
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; HARD-DAG: [[Y:%[0-9]+]](s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
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%6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
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; HARD: [[R:%[0-9]+]](s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
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; SOFT-NOT: G_FCMP
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X0]]
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; SOFT-DAG: %r1 = COPY [[X1]]
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; SOFT-DAG: %r2 = COPY [[Y0]]
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; SOFT-DAG: %r3 = COPY [[Y1]]
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; SOFT-AEABI: BLX $__aeabi_dcmpeq, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT-DEFAULT: BLX $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT: [[RET1:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
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; SOFT-DEFAULT: [[R1:%[0-9]+]](s1) = G_ICMP intpred(eq), [[RET1]](s32), [[ZERO]]
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; SOFT-NOT: G_FCMP
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X0]]
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; SOFT-DAG: %r1 = COPY [[X1]]
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; SOFT-DAG: %r2 = COPY [[Y0]]
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; SOFT-DAG: %r3 = COPY [[Y1]]
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; SOFT-AEABI: BLX $__aeabi_dcmpun, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT-DEFAULT: BLX $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
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; SOFT: [[RET2:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-DEFAULT: [[ZERO:%[0-9]+]](s32) = G_CONSTANT i32 0
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; SOFT-DEFAULT: [[R2:%[0-9]+]](s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
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; SOFT-AEABI: [[R1EXT:%[0-9]+]](s32) = COPY [[RET1]]
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; SOFT-AEABI: [[R2EXT:%[0-9]+]](s32) = COPY [[RET2]]
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; SOFT-DEFAULT: [[R1EXT:%[0-9]+]](s32) = G_ANYEXT [[R1]]
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; SOFT-DEFAULT: [[R2EXT:%[0-9]+]](s32) = G_ANYEXT [[R2]]
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; SOFT: [[REXT:%[0-9]+]](s32) = G_OR [[R1EXT]], [[R2EXT]]
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; SOFT: [[R:%[0-9]+]](s1) = G_TRUNC [[REXT]]
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; SOFT-NOT: G_FCMP
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%7(s32) = G_ZEXT %6(s1)
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; CHECK: [[REXT:%[0-9]+]](s32) = G_ZEXT [[R]](s1)
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%r0 = COPY %7(s32)
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; CHECK: %r0 = COPY [[REXT]]
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BX_RET 14, _, implicit %r0
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...
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