forked from OSchip/llvm-project
500 lines
16 KiB
YAML
500 lines
16 KiB
YAML
# RUN: llc -mtriple arm-linux-gnueabi -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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# RUN: llc -mtriple arm-linux-gnueabi -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-AEABI
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# RUN: llc -mtriple arm-linux-gnu -mattr=+hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
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# RUN: llc -mtriple arm-linux-gnu -mattr=-hwdiv-arm -global-isel -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT,SOFT-DEFAULT
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--- |
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define void @test_sdiv_i32() { ret void }
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define void @test_udiv_i32() { ret void }
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define void @test_sdiv_i16() { ret void }
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define void @test_udiv_i16() { ret void }
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define void @test_sdiv_i8() { ret void }
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define void @test_udiv_i8() { ret void }
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define void @test_srem_i32() { ret void }
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define void @test_urem_i32() { ret void }
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define void @test_srem_i16() { ret void }
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define void @test_urem_i16() { ret void }
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define void @test_srem_i8() { ret void }
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define void @test_urem_i8() { ret void }
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...
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---
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name: test_sdiv_i32
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# CHECK-LABEL: name: test_sdiv_i32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; HWDIV: [[R:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]]
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; SOFT-NOT: G_SDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_SDIV
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%2(s32) = G_SDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_i32
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# CHECK-LABEL: name: test_udiv_i32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; HWDIV: [[R:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]]
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; SOFT-NOT: G_UDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_UDIV
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%2(s32) = G_UDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sdiv_i16
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# CHECK-LABEL: name: test_sdiv_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; SOFT-NOT: G_SDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_SDIV
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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; SOFT-NOT: G_SDIV
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%2(s16) = G_SDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_i16
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# CHECK-LABEL: name: test_udiv_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
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; SOFT-NOT: G_UDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_UDIV
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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; SOFT-NOT: G_UDIV
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%2(s16) = G_UDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_sdiv_i8
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# CHECK-LABEL: name: test_sdiv_i8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8)
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; SOFT-NOT: G_SDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_idiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__divsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_SDIV
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; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
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; SOFT-NOT: G_SDIV
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%2(s8) = G_SDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_udiv_i8
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# CHECK-LABEL: name: test_udiv_i8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8)
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
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; HWDIV: [[R32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
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; SOFT-NOT: G_UDIV
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_uidiv, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT-DEFAULT: BLX $__udivsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_UDIV
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; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
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; SOFT-NOT: G_UDIV
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%2(s8) = G_UDIV %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s8)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_srem_i32
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# CHECK-LABEL: name: test_srem_i32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; HWDIV: [[Q:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]]
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; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]]
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; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]]
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; SOFT-NOT: G_SREM
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
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; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1
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; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_SREM
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%2(s32) = G_SREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_urem_i32
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# CHECK-LABEL: name: test_urem_i32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1
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%0(s32) = COPY %r0
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%1(s32) = COPY %r1
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; HWDIV: [[Q:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]]
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; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]]
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; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]]
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; SOFT-NOT: G_UREM
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X]]
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; SOFT-DAG: %r1 = COPY [[Y]]
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; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1
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; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1
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; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_UREM
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%2(s32) = G_UREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s32)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_srem_i16
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# CHECK-LABEL: name: test_srem_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
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; SOFT-NOT: G_SREM
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
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; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_SREM
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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; SOFT-NOT: G_SREM
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%2(s16) = G_SREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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...
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---
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name: test_urem_i16
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# CHECK-LABEL: name: test_urem_i16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: %r0, %r1
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; CHECK-DAG: [[X:%[0-9]+]](s16) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s16) = COPY %r1
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s16)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s16)
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%0(s16) = COPY %r0
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%1(s16) = COPY %r1
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; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
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; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
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; SOFT-NOT: G_UREM
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; SOFT: ADJCALLSTACKDOWN
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; SOFT-DAG: %r0 = COPY [[X32]]
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; SOFT-DAG: %r1 = COPY [[Y32]]
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; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
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; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
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; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
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; SOFT: ADJCALLSTACKUP
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; SOFT-NOT: G_UREM
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; CHECK: [[R:%[0-9]+]](s16) = G_TRUNC [[R32]]
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; SOFT-NOT: G_UREM
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%2(s16) = G_UREM %0, %1
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; CHECK: %r0 = COPY [[R]]
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%r0 = COPY %2(s16)
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BX_RET 14, _, implicit %r0
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|
...
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---
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name: test_srem_i8
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# CHECK-LABEL: name: test_srem_i8
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
|
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tracksRegLiveness: true
|
|
registers:
|
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- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
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liveins: %r0, %r1
|
|
|
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; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
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; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
|
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; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_SEXT [[X]](s8)
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; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_SEXT [[Y]](s8)
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%0(s8) = COPY %r0
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%1(s8) = COPY %r1
|
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; HWDIV: [[Q32:%[0-9]+]](s32) = G_SDIV [[X32]], [[Y32]]
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; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
|
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; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
|
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; SOFT-NOT: G_SREM
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; SOFT: ADJCALLSTACKDOWN
|
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; SOFT-DAG: %r0 = COPY [[X32]]
|
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; SOFT-DAG: %r1 = COPY [[Y32]]
|
|
; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
|
|
; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-NOT: G_SREM
|
|
; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
|
|
; SOFT-NOT: G_SREM
|
|
%2(s8) = G_SREM %0, %1
|
|
; CHECK: %r0 = COPY [[R]]
|
|
%r0 = COPY %2(s8)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|
|
---
|
|
name: test_urem_i8
|
|
# CHECK-LABEL: name: test_urem_i8
|
|
legalized: false
|
|
# CHECK: legalized: true
|
|
regBankSelected: false
|
|
selected: false
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: _ }
|
|
- { id: 1, class: _ }
|
|
- { id: 2, class: _ }
|
|
body: |
|
|
bb.0:
|
|
liveins: %r0, %r1
|
|
|
|
; CHECK-DAG: [[X:%[0-9]+]](s8) = COPY %r0
|
|
; CHECK-DAG: [[Y:%[0-9]+]](s8) = COPY %r1
|
|
; CHECK-DAG: [[X32:%[0-9]+]](s32) = G_ZEXT [[X]](s8)
|
|
; CHECK-DAG: [[Y32:%[0-9]+]](s32) = G_ZEXT [[Y]](s8)
|
|
%0(s8) = COPY %r0
|
|
%1(s8) = COPY %r1
|
|
; HWDIV: [[Q32:%[0-9]+]](s32) = G_UDIV [[X32]], [[Y32]]
|
|
; HWDIV: [[P32:%[0-9]+]](s32) = G_MUL [[Q32]], [[Y32]]
|
|
; HWDIV: [[R32:%[0-9]+]](s32) = G_SUB [[X32]], [[P32]]
|
|
; SOFT-NOT: G_UREM
|
|
; SOFT: ADJCALLSTACKDOWN
|
|
; SOFT-DAG: %r0 = COPY [[X32]]
|
|
; SOFT-DAG: %r1 = COPY [[Y32]]
|
|
; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-AEABI: [[R32:%[0-9]+]](s32) = COPY %r1
|
|
; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
|
|
; SOFT-DEFAULT: [[R32:%[0-9]+]](s32) = COPY %r0
|
|
; SOFT: ADJCALLSTACKUP
|
|
; SOFT-NOT: G_UREM
|
|
; CHECK: [[R:%[0-9]+]](s8) = G_TRUNC [[R32]]
|
|
; SOFT-NOT: G_UREM
|
|
%2(s8) = G_UREM %0, %1
|
|
; CHECK: %r0 = COPY [[R]]
|
|
%r0 = COPY %2(s8)
|
|
BX_RET 14, _, implicit %r0
|
|
...
|