forked from OSchip/llvm-project
1013 lines
42 KiB
C++
1013 lines
42 KiB
C++
//===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of TargetFrameLowering class.
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//
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// On AArch64, stack frames are structured as follows:
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//
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// The stack grows downward.
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//
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// All of the individual frame areas on the frame below are optional, i.e. it's
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// possible to create a function so that the particular area isn't present
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// in the frame.
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//
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// At function entry, the "frame" looks as follows:
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//
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// | | Higher address
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// |-----------------------------------|
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// | |
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// | arguments passed on the stack |
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// | |
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// |-----------------------------------| <- sp
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// | | Lower address
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//
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//
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// After the prologue has run, the frame has the following general structure.
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// Note that this doesn't depict the case where a red-zone is used. Also,
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// technically the last frame area (VLAs) doesn't get created until in the
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// main function body, after the prologue is run. However, it's depicted here
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// for completeness.
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//
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// | | Higher address
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// |-----------------------------------|
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// | |
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// | arguments passed on the stack |
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// | |
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// |-----------------------------------|
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// | |
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// | prev_fp, prev_lr |
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// | (a.k.a. "frame record") |
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// |-----------------------------------| <- fp(=x29)
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// | |
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// | other callee-saved registers |
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// | |
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// |-----------------------------------|
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// |.empty.space.to.make.part.below....|
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// |.aligned.in.case.it.needs.more.than| (size of this area is unknown at
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// |.the.standard.16-byte.alignment....| compile time; if present)
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// |-----------------------------------|
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// | |
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// | local variables of fixed size |
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// | including spill slots |
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// |-----------------------------------| <- bp(not defined by ABI,
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// |.variable-sized.local.variables....| LLVM chooses X19)
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// |.(VLAs)............................| (size of this area is unknown at
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// |...................................| compile time)
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// |-----------------------------------| <- sp
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// | | Lower address
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//
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//
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// To access the data in a frame, at-compile time, a constant offset must be
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// computable from one of the pointers (fp, bp, sp) to access it. The size
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// of the areas with a dotted background cannot be computed at compile-time
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// if they are present, making it required to have all three of fp, bp and
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// sp to be set up to be able to access all contents in the frame areas,
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// assuming all of the frame areas are non-empty.
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//
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// For most functions, some of the frame areas are empty. For those functions,
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// it may not be necessary to set up fp or bp:
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// * A base pointer is definitely needed when there are both VLAs and local
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// variables with more-than-default alignment requirements.
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// * A frame pointer is definitely needed when there are local variables with
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// more-than-default alignment requirements.
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//
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// In some cases when a base pointer is not strictly needed, it is generated
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// anyway when offsets from the frame pointer to access local variables become
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// so large that the offset can't be encoded in the immediate fields of loads
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// or stores.
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//
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// FIXME: also explain the redzone concept.
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// FIXME: also explain the concept of reserved call frames.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64FrameLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "frame-info"
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static cl::opt<bool> EnableRedZone("aarch64-redzone",
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cl::desc("enable use of redzone on AArch64"),
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cl::init(false), cl::Hidden);
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STATISTIC(NumRedZoneFunctions, "Number of functions using red zone");
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bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
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if (!EnableRedZone)
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return false;
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// Don't use the red zone if the function explicitly asks us not to.
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// This is typically used for kernel code.
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if (MF.getFunction()->hasFnAttribute(Attribute::NoRedZone))
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return false;
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
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unsigned NumBytes = AFI->getLocalStackSize();
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// Note: currently hasFP() is always true for hasCalls(), but that's an
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// implementation detail of the current code, not a strict requirement,
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// so stay safe here and check both.
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if (MFI->hasCalls() || hasFP(MF) || NumBytes > 128)
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return false;
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return true;
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}
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/// hasFP - Return true if the specified function should have a dedicated frame
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/// pointer register.
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bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
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return (MFI->hasCalls() || MFI->hasVarSizedObjects() ||
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MFI->isFrameAddressTaken() || MFI->hasStackMap() ||
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MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF));
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}
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/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
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/// not required, we reserve argument space for call sites in the function
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/// immediately on entry to the current function. This eliminates the need for
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/// add/sub sp brackets around call sites. Returns true if the call frame is
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/// included as part of the stack frame.
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bool
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AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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void AArch64FrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const AArch64InstrInfo *TII =
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static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
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DebugLoc DL = I->getDebugLoc();
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unsigned Opc = I->getOpcode();
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bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
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uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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if (!TFI->hasReservedCallFrame(MF)) {
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unsigned Align = getStackAlignment();
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int64_t Amount = I->getOperand(0).getImm();
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Amount = RoundUpToAlignment(Amount, Align);
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if (!IsDestroy)
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Amount = -Amount;
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// N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
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// doesn't have to pop anything), then the first operand will be zero too so
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// this adjustment is a no-op.
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if (CalleePopAmount == 0) {
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// FIXME: in-function stack adjustment for calls is limited to 24-bits
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// because there's no guaranteed temporary register available.
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//
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// ADD/SUB (immediate) has only LSL #0 and LSL #12 available.
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// 1) For offset <= 12-bit, we use LSL #0
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// 2) For 12-bit <= offset <= 24-bit, we use two instructions. One uses
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// LSL #0, and the other uses LSL #12.
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//
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// Mostly call frames will be allocated at the start of a function so
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// this is OK, but it is a limitation that needs dealing with.
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assert(Amount > -0xffffff && Amount < 0xffffff && "call frame too large");
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emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
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}
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} else if (CalleePopAmount != 0) {
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// If the calling convention demands that the callee pops arguments from the
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// stack, we want to add it back if we have a reserved call frame.
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assert(CalleePopAmount < 0xffffff && "call frame too large");
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emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
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TII);
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}
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MBB.erase(I);
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}
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void AArch64FrameLowering::emitCalleeSavedFrameMoves(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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unsigned FramePtr) const {
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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// Add callee saved registers to move list.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.empty())
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return;
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const DataLayout &TD = MF.getDataLayout();
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bool HasFP = hasFP(MF);
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// Calculate amount of bytes used for return address storing.
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int stackGrowth = -TD.getPointerSize(0);
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// Calculate offsets.
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int64_t saveAreaOffset = (HasFP ? 2 : 1) * stackGrowth;
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unsigned TotalSkipped = 0;
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for (const auto &Info : CSI) {
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unsigned Reg = Info.getReg();
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int64_t Offset = MFI->getObjectOffset(Info.getFrameIdx()) -
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getOffsetOfLocalArea() + saveAreaOffset;
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// Don't output a new CFI directive if we're re-saving the frame pointer or
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// link register. This happens when the PrologEpilogInserter has inserted an
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// extra "STP" of the frame pointer and link register -- the "emitPrologue"
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// method automatically generates the directives when frame pointers are
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// used. If we generate CFI directives for the extra "STP"s, the linker will
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// lose track of the correct values for the frame pointer and link register.
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if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
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TotalSkipped += stackGrowth;
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continue;
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}
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unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, DwarfReg, Offset - TotalSkipped));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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}
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/// Get FPOffset by analyzing the first instruction.
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static int getFPOffsetInPrologue(MachineInstr *MBBI) {
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// First instruction must a) allocate the stack and b) have an immediate
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// that is a multiple of -2.
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assert(((MBBI->getOpcode() == AArch64::STPXpre ||
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MBBI->getOpcode() == AArch64::STPDpre) &&
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MBBI->getOperand(3).getReg() == AArch64::SP &&
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MBBI->getOperand(4).getImm() < 0 &&
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(MBBI->getOperand(4).getImm() & 1) == 0));
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// Frame pointer is fp = sp - 16. Since the STPXpre subtracts the space
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// required for the callee saved register area we get the frame pointer
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// by addding that offset - 16 = -getImm()*8 - 2*8 = -(getImm() + 2) * 8.
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int FPOffset = -(MBBI->getOperand(4).getImm() + 2) * 8;
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assert(FPOffset >= 0 && "Bad Framepointer Offset");
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return FPOffset;
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}
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static bool isCSSave(MachineInstr *MBBI) {
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return MBBI->getOpcode() == AArch64::STPXi ||
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MBBI->getOpcode() == AArch64::STPDi ||
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MBBI->getOpcode() == AArch64::STPXpre ||
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MBBI->getOpcode() == AArch64::STPDpre;
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}
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void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.begin();
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *Fn = MF.getFunction();
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const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
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MF.getSubtarget().getRegisterInfo());
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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MachineModuleInfo &MMI = MF.getMMI();
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AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
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bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
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bool HasFP = hasFP(MF);
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc DL;
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// All calls are tail calls in GHC calling conv, and functions have no
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// prologue/epilogue.
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if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
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return;
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int NumBytes = (int)MFI->getStackSize();
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if (!AFI->hasStackFrame()) {
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assert(!HasFP && "unexpected function without stack frame but with FP");
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// All of the stack allocation is for locals.
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AFI->setLocalStackSize(NumBytes);
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// Label used to tie together the PROLOG_LABEL and the MachineMoves.
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MCSymbol *FrameLabel = MMI.getContext().createTempSymbol();
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// REDZONE: If the stack size is less than 128 bytes, we don't need
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// to actually allocate.
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if (NumBytes && !canUseRedZone(MF)) {
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emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
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MachineInstr::FrameSetup);
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// Encode the stack size of the leaf function.
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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} else if (NumBytes) {
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++NumRedZoneFunctions;
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}
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return;
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}
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// Only set up FP if we actually need to.
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int FPOffset = 0;
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if (HasFP)
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FPOffset = getFPOffsetInPrologue(MBBI);
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// Move past the saves of the callee-saved registers.
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while (isCSSave(MBBI)) {
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++MBBI;
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NumBytes -= 16;
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}
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assert(NumBytes >= 0 && "Negative stack allocation size!?");
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if (HasFP) {
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// Issue sub fp, sp, FPOffset or
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// mov fp,sp when FPOffset is zero.
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// Note: All stores of callee-saved registers are marked as "FrameSetup".
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// This code marks the instruction(s) that set the FP also.
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emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
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MachineInstr::FrameSetup);
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}
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// All of the remaining stack allocations are for locals.
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AFI->setLocalStackSize(NumBytes);
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// Allocate space for the rest of the frame.
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const unsigned Alignment = MFI->getMaxAlignment();
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const bool NeedsRealignment = RegInfo->needsStackRealignment(MF);
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unsigned scratchSPReg = AArch64::SP;
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if (NumBytes && NeedsRealignment) {
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// Use the first callee-saved register as a scratch register.
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scratchSPReg = AArch64::X9;
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}
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// If we're a leaf function, try using the red zone.
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if (NumBytes && !canUseRedZone(MF))
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// FIXME: in the case of dynamic re-alignment, NumBytes doesn't have
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// the correct value here, as NumBytes also includes padding bytes,
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// which shouldn't be counted here.
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emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
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MachineInstr::FrameSetup);
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if (NumBytes && NeedsRealignment) {
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const unsigned NrBitsToZero = countTrailingZeros(Alignment);
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assert(NrBitsToZero > 1);
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assert(scratchSPReg != AArch64::SP);
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// SUB X9, SP, NumBytes
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// -- X9 is temporary register, so shouldn't contain any live data here,
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// -- free to use. This is already produced by emitFrameOffset above.
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// AND SP, X9, 0b11111...0000
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// The logical immediates have a non-trivial encoding. The following
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// formula computes the encoded immediate with all ones but
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// NrBitsToZero zero bits as least significant bits.
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uint32_t andMaskEncoded =
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(1 <<12) // = N
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| ((64-NrBitsToZero) << 6) // immr
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| ((64-NrBitsToZero-1) << 0) // imms
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;
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
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.addReg(scratchSPReg, RegState::Kill)
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.addImm(andMaskEncoded);
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}
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// If we need a base pointer, set it up here. It's whatever the value of the
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// stack pointer is at this point. Any variable size objects will be allocated
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// after this, so we can still use the base pointer to reference locals.
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//
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// FIXME: Clarify FrameSetup flags here.
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// Note: Use emitFrameOffset() like above for FP if the FrameSetup flag is
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// needed.
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if (RegInfo->hasBasePointer(MF)) {
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TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
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false);
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}
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if (needsFrameMoves) {
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const DataLayout &TD = MF.getDataLayout();
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const int StackGrowth = -TD.getPointerSize(0);
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unsigned FramePtr = RegInfo->getFrameRegister(MF);
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// An example of the prologue:
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//
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// .globl __foo
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// .align 2
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// __foo:
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// Ltmp0:
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// .cfi_startproc
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// .cfi_personality 155, ___gxx_personality_v0
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// Leh_func_begin:
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// .cfi_lsda 16, Lexception33
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//
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// stp xa,bx, [sp, -#offset]!
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// ...
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// stp x28, x27, [sp, #offset-32]
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// stp fp, lr, [sp, #offset-16]
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// add fp, sp, #offset - 16
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// sub sp, sp, #1360
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//
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// The Stack:
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// +-------------------------------------------+
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// 10000 | ........ | ........ | ........ | ........ |
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// 10004 | ........ | ........ | ........ | ........ |
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// +-------------------------------------------+
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// 10008 | ........ | ........ | ........ | ........ |
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// 1000c | ........ | ........ | ........ | ........ |
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// +===========================================+
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// 10010 | X28 Register |
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// 10014 | X28 Register |
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// +-------------------------------------------+
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// 10018 | X27 Register |
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// 1001c | X27 Register |
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// +===========================================+
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// 10020 | Frame Pointer |
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// 10024 | Frame Pointer |
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// +-------------------------------------------+
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// 10028 | Link Register |
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// 1002c | Link Register |
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// +===========================================+
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// 10030 | ........ | ........ | ........ | ........ |
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// 10034 | ........ | ........ | ........ | ........ |
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// +-------------------------------------------+
|
|
// 10038 | ........ | ........ | ........ | ........ |
|
|
// 1003c | ........ | ........ | ........ | ........ |
|
|
// +-------------------------------------------+
|
|
//
|
|
// [sp] = 10030 :: >>initial value<<
|
|
// sp = 10020 :: stp fp, lr, [sp, #-16]!
|
|
// fp = sp == 10020 :: mov fp, sp
|
|
// [sp] == 10020 :: stp x28, x27, [sp, #-16]!
|
|
// sp == 10010 :: >>final value<<
|
|
//
|
|
// The frame pointer (w29) points to address 10020. If we use an offset of
|
|
// '16' from 'w29', we get the CFI offsets of -8 for w30, -16 for w29, -24
|
|
// for w27, and -32 for w28:
|
|
//
|
|
// Ltmp1:
|
|
// .cfi_def_cfa w29, 16
|
|
// Ltmp2:
|
|
// .cfi_offset w30, -8
|
|
// Ltmp3:
|
|
// .cfi_offset w29, -16
|
|
// Ltmp4:
|
|
// .cfi_offset w27, -24
|
|
// Ltmp5:
|
|
// .cfi_offset w28, -32
|
|
|
|
if (HasFP) {
|
|
// Define the current CFA rule to use the provided FP.
|
|
unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth));
|
|
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
|
|
.addCFIIndex(CFIIndex)
|
|
.setMIFlags(MachineInstr::FrameSetup);
|
|
|
|
// Record the location of the stored LR
|
|
unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
|
|
CFIIndex = MMI.addFrameInst(
|
|
MCCFIInstruction::createOffset(nullptr, LR, StackGrowth));
|
|
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
|
|
.addCFIIndex(CFIIndex)
|
|
.setMIFlags(MachineInstr::FrameSetup);
|
|
|
|
// Record the location of the stored FP
|
|
CFIIndex = MMI.addFrameInst(
|
|
MCCFIInstruction::createOffset(nullptr, Reg, 2 * StackGrowth));
|
|
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
|
|
.addCFIIndex(CFIIndex)
|
|
.setMIFlags(MachineInstr::FrameSetup);
|
|
} else {
|
|
// Encode the stack size of the leaf function.
|
|
unsigned CFIIndex = MMI.addFrameInst(
|
|
MCCFIInstruction::createDefCfaOffset(nullptr, -MFI->getStackSize()));
|
|
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
|
|
.addCFIIndex(CFIIndex)
|
|
.setMIFlags(MachineInstr::FrameSetup);
|
|
}
|
|
|
|
// Now emit the moves for whatever callee saved regs we have.
|
|
emitCalleeSavedFrameMoves(MBB, MBBI, FramePtr);
|
|
}
|
|
}
|
|
|
|
static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
|
|
for (unsigned i = 0; CSRegs[i]; ++i)
|
|
if (Reg == CSRegs[i])
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
|
|
unsigned RtIdx = 0;
|
|
if (MI->getOpcode() == AArch64::LDPXpost ||
|
|
MI->getOpcode() == AArch64::LDPDpost)
|
|
RtIdx = 1;
|
|
|
|
if (MI->getOpcode() == AArch64::LDPXpost ||
|
|
MI->getOpcode() == AArch64::LDPDpost ||
|
|
MI->getOpcode() == AArch64::LDPXi || MI->getOpcode() == AArch64::LDPDi) {
|
|
if (!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
|
|
!isCalleeSavedRegister(MI->getOperand(RtIdx + 1).getReg(), CSRegs) ||
|
|
MI->getOperand(RtIdx + 2).getReg() != AArch64::SP)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
|
|
MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const AArch64InstrInfo *TII =
|
|
static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
|
|
const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
|
|
MF.getSubtarget().getRegisterInfo());
|
|
DebugLoc DL;
|
|
bool IsTailCallReturn = false;
|
|
if (MBB.end() != MBBI) {
|
|
DL = MBBI->getDebugLoc();
|
|
unsigned RetOpcode = MBBI->getOpcode();
|
|
IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
|
|
RetOpcode == AArch64::TCRETURNri;
|
|
}
|
|
int NumBytes = MFI->getStackSize();
|
|
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
|
|
|
|
// All calls are tail calls in GHC calling conv, and functions have no
|
|
// prologue/epilogue.
|
|
if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
|
|
return;
|
|
|
|
// Initial and residual are named for consistency with the prologue. Note that
|
|
// in the epilogue, the residual adjustment is executed first.
|
|
uint64_t ArgumentPopSize = 0;
|
|
if (IsTailCallReturn) {
|
|
MachineOperand &StackAdjust = MBBI->getOperand(1);
|
|
|
|
// For a tail-call in a callee-pops-arguments environment, some or all of
|
|
// the stack may actually be in use for the call's arguments, this is
|
|
// calculated during LowerCall and consumed here...
|
|
ArgumentPopSize = StackAdjust.getImm();
|
|
} else {
|
|
// ... otherwise the amount to pop is *all* of the argument space,
|
|
// conveniently stored in the MachineFunctionInfo by
|
|
// LowerFormalArguments. This will, of course, be zero for the C calling
|
|
// convention.
|
|
ArgumentPopSize = AFI->getArgumentStackToRestore();
|
|
}
|
|
|
|
// The stack frame should be like below,
|
|
//
|
|
// ---------------------- ---
|
|
// | | |
|
|
// | BytesInStackArgArea| CalleeArgStackSize
|
|
// | (NumReusableBytes) | (of tail call)
|
|
// | | ---
|
|
// | | |
|
|
// ---------------------| --- |
|
|
// | | | |
|
|
// | CalleeSavedReg | | |
|
|
// | (NumRestores * 16) | | |
|
|
// | | | |
|
|
// ---------------------| | NumBytes
|
|
// | | StackSize (StackAdjustUp)
|
|
// | LocalStackSize | | |
|
|
// | (covering callee | | |
|
|
// | args) | | |
|
|
// | | | |
|
|
// ---------------------- --- ---
|
|
//
|
|
// So NumBytes = StackSize + BytesInStackArgArea - CalleeArgStackSize
|
|
// = StackSize + ArgumentPopSize
|
|
//
|
|
// AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps
|
|
// it as the 2nd argument of AArch64ISD::TC_RETURN.
|
|
NumBytes += ArgumentPopSize;
|
|
|
|
unsigned NumRestores = 0;
|
|
// Move past the restores of the callee-saved registers.
|
|
MachineBasicBlock::iterator LastPopI = MBB.getFirstTerminator();
|
|
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
|
|
if (LastPopI != MBB.begin()) {
|
|
do {
|
|
++NumRestores;
|
|
--LastPopI;
|
|
} while (LastPopI != MBB.begin() && isCSRestore(LastPopI, CSRegs));
|
|
if (!isCSRestore(LastPopI, CSRegs)) {
|
|
++LastPopI;
|
|
--NumRestores;
|
|
}
|
|
}
|
|
NumBytes -= NumRestores * 16;
|
|
assert(NumBytes >= 0 && "Negative stack allocation size!?");
|
|
|
|
if (!hasFP(MF)) {
|
|
// If this was a redzone leaf function, we don't need to restore the
|
|
// stack pointer.
|
|
if (!canUseRedZone(MF))
|
|
emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes,
|
|
TII);
|
|
return;
|
|
}
|
|
|
|
// Restore the original stack pointer.
|
|
// FIXME: Rather than doing the math here, we should instead just use
|
|
// non-post-indexed loads for the restores if we aren't actually going to
|
|
// be able to save any instructions.
|
|
if (NumBytes || MFI->hasVarSizedObjects())
|
|
emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
|
|
-(NumRestores - 1) * 16, TII, MachineInstr::NoFlags);
|
|
}
|
|
|
|
/// getFrameIndexReference - Provide a base+offset reference to an FI slot for
|
|
/// debug info. It's the same as what we use for resolving the code-gen
|
|
/// references for now. FIXME: This can go wrong when references are
|
|
/// SP-relative and simple call frames aren't used.
|
|
int AArch64FrameLowering::getFrameIndexReference(const MachineFunction &MF,
|
|
int FI,
|
|
unsigned &FrameReg) const {
|
|
return resolveFrameIndexReference(MF, FI, FrameReg);
|
|
}
|
|
|
|
int AArch64FrameLowering::resolveFrameIndexReference(const MachineFunction &MF,
|
|
int FI, unsigned &FrameReg,
|
|
bool PreferFP) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
|
|
MF.getSubtarget().getRegisterInfo());
|
|
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
|
|
int FPOffset = MFI->getObjectOffset(FI) + 16;
|
|
int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
|
|
bool isFixed = MFI->isFixedObjectIndex(FI);
|
|
|
|
// Use frame pointer to reference fixed objects. Use it for locals if
|
|
// there are VLAs or a dynamically realigned SP (and thus the SP isn't
|
|
// reliable as a base). Make sure useFPForScavengingIndex() does the
|
|
// right thing for the emergency spill slot.
|
|
bool UseFP = false;
|
|
if (AFI->hasStackFrame()) {
|
|
// Note: Keeping the following as multiple 'if' statements rather than
|
|
// merging to a single expression for readability.
|
|
//
|
|
// Argument access should always use the FP.
|
|
if (isFixed) {
|
|
UseFP = hasFP(MF);
|
|
} else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) &&
|
|
!RegInfo->needsStackRealignment(MF)) {
|
|
// Use SP or FP, whichever gives us the best chance of the offset
|
|
// being in range for direct access. If the FPOffset is positive,
|
|
// that'll always be best, as the SP will be even further away.
|
|
// If the FPOffset is negative, we have to keep in mind that the
|
|
// available offset range for negative offsets is smaller than for
|
|
// positive ones. If we have variable sized objects, we're stuck with
|
|
// using the FP regardless, though, as the SP offset is unknown
|
|
// and we don't have a base pointer available. If an offset is
|
|
// available via the FP and the SP, use whichever is closest.
|
|
if (PreferFP || MFI->hasVarSizedObjects() || FPOffset >= 0 ||
|
|
(FPOffset >= -256 && Offset > -FPOffset))
|
|
UseFP = true;
|
|
}
|
|
}
|
|
|
|
assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) &&
|
|
"In the presence of dynamic stack pointer realignment, "
|
|
"non-argument objects cannot be accessed through the frame pointer");
|
|
|
|
if (UseFP) {
|
|
FrameReg = RegInfo->getFrameRegister(MF);
|
|
return FPOffset;
|
|
}
|
|
|
|
// Use the base pointer if we have one.
|
|
if (RegInfo->hasBasePointer(MF))
|
|
FrameReg = RegInfo->getBaseRegister();
|
|
else {
|
|
FrameReg = AArch64::SP;
|
|
// If we're using the red zone for this function, the SP won't actually
|
|
// be adjusted, so the offsets will be negative. They're also all
|
|
// within range of the signed 9-bit immediate instructions.
|
|
if (canUseRedZone(MF))
|
|
Offset -= AFI->getLocalStackSize();
|
|
}
|
|
|
|
return Offset;
|
|
}
|
|
|
|
static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
|
|
if (Reg != AArch64::LR)
|
|
return getKillRegState(true);
|
|
|
|
// LR maybe referred to later by an @llvm.returnaddress intrinsic.
|
|
bool LRLiveIn = MF.getRegInfo().isLiveIn(AArch64::LR);
|
|
bool LRKill = !(LRLiveIn && MF.getFrameInfo()->isReturnAddressTaken());
|
|
return getKillRegState(LRKill);
|
|
}
|
|
|
|
bool AArch64FrameLowering::spillCalleeSavedRegisters(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
|
unsigned Count = CSI.size();
|
|
DebugLoc DL;
|
|
assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
|
|
|
|
for (unsigned i = 0; i < Count; i += 2) {
|
|
unsigned idx = Count - i - 2;
|
|
unsigned Reg1 = CSI[idx].getReg();
|
|
unsigned Reg2 = CSI[idx + 1].getReg();
|
|
// GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
|
|
// list to come in sorted by frame index so that we can issue the store
|
|
// pair instructions directly. Assert if we see anything otherwise.
|
|
//
|
|
// The order of the registers in the list is controlled by
|
|
// getCalleeSavedRegs(), so they will always be in-order, as well.
|
|
assert(CSI[idx].getFrameIdx() + 1 == CSI[idx + 1].getFrameIdx() &&
|
|
"Out of order callee saved regs!");
|
|
unsigned StrOpc;
|
|
assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
|
|
assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
|
|
// Issue sequence of non-sp increment and pi sp spills for cs regs. The
|
|
// first spill is a pre-increment that allocates the stack.
|
|
// For example:
|
|
// stp x22, x21, [sp, #-48]! // addImm(-6)
|
|
// stp x20, x19, [sp, #16] // addImm(+2)
|
|
// stp fp, lr, [sp, #32] // addImm(+4)
|
|
// Rationale: This sequence saves uop updates compared to a sequence of
|
|
// pre-increment spills like stp xi,xj,[sp,#-16]!
|
|
// Note: Similar rational and sequence for restores in epilog.
|
|
if (AArch64::GPR64RegClass.contains(Reg1)) {
|
|
assert(AArch64::GPR64RegClass.contains(Reg2) &&
|
|
"Expected GPR64 callee-saved register pair!");
|
|
// For first spill use pre-increment store.
|
|
if (i == 0)
|
|
StrOpc = AArch64::STPXpre;
|
|
else
|
|
StrOpc = AArch64::STPXi;
|
|
} else if (AArch64::FPR64RegClass.contains(Reg1)) {
|
|
assert(AArch64::FPR64RegClass.contains(Reg2) &&
|
|
"Expected FPR64 callee-saved register pair!");
|
|
// For first spill use pre-increment store.
|
|
if (i == 0)
|
|
StrOpc = AArch64::STPDpre;
|
|
else
|
|
StrOpc = AArch64::STPDi;
|
|
} else
|
|
llvm_unreachable("Unexpected callee saved register!");
|
|
DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
|
|
<< TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
|
|
<< ", " << CSI[idx + 1].getFrameIdx() << ")\n");
|
|
// Compute offset: i = 0 => offset = -Count;
|
|
// i = 2 => offset = -(Count - 2) + Count = 2 = i; etc.
|
|
const int Offset = (i == 0) ? -Count : i;
|
|
assert((Offset >= -64 && Offset <= 63) &&
|
|
"Offset out of bounds for STP immediate");
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
|
|
if (StrOpc == AArch64::STPDpre || StrOpc == AArch64::STPXpre)
|
|
MIB.addReg(AArch64::SP, RegState::Define);
|
|
|
|
MBB.addLiveIn(Reg1);
|
|
MBB.addLiveIn(Reg2);
|
|
MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
|
|
.addReg(Reg1, getPrologueDeath(MF, Reg1))
|
|
.addReg(AArch64::SP)
|
|
.addImm(Offset) // [sp, #offset * 8], where factor * 8 is implicit
|
|
.setMIFlag(MachineInstr::FrameSetup);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AArch64FrameLowering::restoreCalleeSavedRegisters(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
|
unsigned Count = CSI.size();
|
|
DebugLoc DL;
|
|
assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
|
|
|
|
if (MI != MBB.end())
|
|
DL = MI->getDebugLoc();
|
|
|
|
for (unsigned i = 0; i < Count; i += 2) {
|
|
unsigned Reg1 = CSI[i].getReg();
|
|
unsigned Reg2 = CSI[i + 1].getReg();
|
|
// GPRs and FPRs are saved in pairs of 64-bit regs. We expect the CSI
|
|
// list to come in sorted by frame index so that we can issue the store
|
|
// pair instructions directly. Assert if we see anything otherwise.
|
|
assert(CSI[i].getFrameIdx() + 1 == CSI[i + 1].getFrameIdx() &&
|
|
"Out of order callee saved regs!");
|
|
// Issue sequence of non-sp increment and sp-pi restores for cs regs. Only
|
|
// the last load is sp-pi post-increment and de-allocates the stack:
|
|
// For example:
|
|
// ldp fp, lr, [sp, #32] // addImm(+4)
|
|
// ldp x20, x19, [sp, #16] // addImm(+2)
|
|
// ldp x22, x21, [sp], #48 // addImm(+6)
|
|
// Note: see comment in spillCalleeSavedRegisters()
|
|
unsigned LdrOpc;
|
|
|
|
assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!");
|
|
assert((i & 1) == 0 && "Odd index for callee-saved reg spill!");
|
|
if (AArch64::GPR64RegClass.contains(Reg1)) {
|
|
assert(AArch64::GPR64RegClass.contains(Reg2) &&
|
|
"Expected GPR64 callee-saved register pair!");
|
|
if (i == Count - 2)
|
|
LdrOpc = AArch64::LDPXpost;
|
|
else
|
|
LdrOpc = AArch64::LDPXi;
|
|
} else if (AArch64::FPR64RegClass.contains(Reg1)) {
|
|
assert(AArch64::FPR64RegClass.contains(Reg2) &&
|
|
"Expected FPR64 callee-saved register pair!");
|
|
if (i == Count - 2)
|
|
LdrOpc = AArch64::LDPDpost;
|
|
else
|
|
LdrOpc = AArch64::LDPDi;
|
|
} else
|
|
llvm_unreachable("Unexpected callee saved register!");
|
|
DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
|
|
<< TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
|
|
<< ", " << CSI[i + 1].getFrameIdx() << ")\n");
|
|
|
|
// Compute offset: i = 0 => offset = Count - 2; i = 2 => offset = Count - 4;
|
|
// etc.
|
|
const int Offset = (i == Count - 2) ? Count : Count - i - 2;
|
|
assert((Offset >= -64 && Offset <= 63) &&
|
|
"Offset out of bounds for LDP immediate");
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
|
|
if (LdrOpc == AArch64::LDPXpost || LdrOpc == AArch64::LDPDpost)
|
|
MIB.addReg(AArch64::SP, RegState::Define);
|
|
|
|
MIB.addReg(Reg2, getDefRegState(true))
|
|
.addReg(Reg1, getDefRegState(true))
|
|
.addReg(AArch64::SP)
|
|
.addImm(Offset); // [sp], #offset * 8 or [sp, #offset * 8]
|
|
// where the factor * 8 is implicit
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
|
|
BitVector &SavedRegs,
|
|
RegScavenger *RS) const {
|
|
// All calls are tail calls in GHC calling conv, and functions have no
|
|
// prologue/epilogue.
|
|
if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
|
|
return;
|
|
|
|
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
|
|
const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>(
|
|
MF.getSubtarget().getRegisterInfo());
|
|
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
|
|
SmallVector<unsigned, 4> UnspilledCSGPRs;
|
|
SmallVector<unsigned, 4> UnspilledCSFPRs;
|
|
|
|
// The frame record needs to be created by saving the appropriate registers
|
|
if (hasFP(MF)) {
|
|
SavedRegs.set(AArch64::FP);
|
|
SavedRegs.set(AArch64::LR);
|
|
}
|
|
|
|
// Spill the BasePtr if it's used. Do this first thing so that the
|
|
// getCalleeSavedRegs() below will get the right answer.
|
|
if (RegInfo->hasBasePointer(MF))
|
|
SavedRegs.set(RegInfo->getBaseRegister());
|
|
|
|
if (RegInfo->needsStackRealignment(MF) && !RegInfo->hasBasePointer(MF))
|
|
SavedRegs.set(AArch64::X9);
|
|
|
|
// If any callee-saved registers are used, the frame cannot be eliminated.
|
|
unsigned NumGPRSpilled = 0;
|
|
unsigned NumFPRSpilled = 0;
|
|
bool ExtraCSSpill = false;
|
|
bool CanEliminateFrame = true;
|
|
DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:");
|
|
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
|
|
|
|
// Check pairs of consecutive callee-saved registers.
|
|
for (unsigned i = 0; CSRegs[i]; i += 2) {
|
|
assert(CSRegs[i + 1] && "Odd number of callee-saved registers!");
|
|
|
|
const unsigned OddReg = CSRegs[i];
|
|
const unsigned EvenReg = CSRegs[i + 1];
|
|
assert((AArch64::GPR64RegClass.contains(OddReg) &&
|
|
AArch64::GPR64RegClass.contains(EvenReg)) ^
|
|
(AArch64::FPR64RegClass.contains(OddReg) &&
|
|
AArch64::FPR64RegClass.contains(EvenReg)) &&
|
|
"Register class mismatch!");
|
|
|
|
const bool OddRegUsed = SavedRegs.test(OddReg);
|
|
const bool EvenRegUsed = SavedRegs.test(EvenReg);
|
|
|
|
// Early exit if none of the registers in the register pair is actually
|
|
// used.
|
|
if (!OddRegUsed && !EvenRegUsed) {
|
|
if (AArch64::GPR64RegClass.contains(OddReg)) {
|
|
UnspilledCSGPRs.push_back(OddReg);
|
|
UnspilledCSGPRs.push_back(EvenReg);
|
|
} else {
|
|
UnspilledCSFPRs.push_back(OddReg);
|
|
UnspilledCSFPRs.push_back(EvenReg);
|
|
}
|
|
continue;
|
|
}
|
|
|
|
unsigned Reg = AArch64::NoRegister;
|
|
// If only one of the registers of the register pair is used, make sure to
|
|
// mark the other one as used as well.
|
|
if (OddRegUsed ^ EvenRegUsed) {
|
|
// Find out which register is the additional spill.
|
|
Reg = OddRegUsed ? EvenReg : OddReg;
|
|
SavedRegs.set(Reg);
|
|
}
|
|
|
|
DEBUG(dbgs() << ' ' << PrintReg(OddReg, RegInfo));
|
|
DEBUG(dbgs() << ' ' << PrintReg(EvenReg, RegInfo));
|
|
|
|
assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) ||
|
|
(RegInfo->getEncodingValue(OddReg) + 1 ==
|
|
RegInfo->getEncodingValue(EvenReg))) &&
|
|
"Register pair of non-adjacent registers!");
|
|
if (AArch64::GPR64RegClass.contains(OddReg)) {
|
|
NumGPRSpilled += 2;
|
|
// If it's not a reserved register, we can use it in lieu of an
|
|
// emergency spill slot for the register scavenger.
|
|
// FIXME: It would be better to instead keep looking and choose another
|
|
// unspilled register that isn't reserved, if there is one.
|
|
if (Reg != AArch64::NoRegister && !RegInfo->isReservedReg(MF, Reg))
|
|
ExtraCSSpill = true;
|
|
} else
|
|
NumFPRSpilled += 2;
|
|
|
|
CanEliminateFrame = false;
|
|
}
|
|
|
|
// FIXME: Set BigStack if any stack slot references may be out of range.
|
|
// For now, just conservatively guestimate based on unscaled indexing
|
|
// range. We'll end up allocating an unnecessary spill slot a lot, but
|
|
// realistically that's not a big deal at this stage of the game.
|
|
// The CSR spill slots have not been allocated yet, so estimateStackSize
|
|
// won't include them.
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
unsigned CFSize =
|
|
MFI->estimateStackSize(MF) + 8 * (NumGPRSpilled + NumFPRSpilled);
|
|
DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
|
|
bool BigStack = (CFSize >= 256);
|
|
if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
|
|
AFI->setHasStackFrame(true);
|
|
|
|
// Estimate if we might need to scavenge a register at some point in order
|
|
// to materialize a stack offset. If so, either spill one additional
|
|
// callee-saved register or reserve a special spill slot to facilitate
|
|
// register scavenging. If we already spilled an extra callee-saved register
|
|
// above to keep the number of spills even, we don't need to do anything else
|
|
// here.
|
|
if (BigStack && !ExtraCSSpill) {
|
|
|
|
// If we're adding a register to spill here, we have to add two of them
|
|
// to keep the number of regs to spill even.
|
|
assert(((UnspilledCSGPRs.size() & 1) == 0) && "Odd number of registers!");
|
|
unsigned Count = 0;
|
|
while (!UnspilledCSGPRs.empty() && Count < 2) {
|
|
unsigned Reg = UnspilledCSGPRs.back();
|
|
UnspilledCSGPRs.pop_back();
|
|
DEBUG(dbgs() << "Spilling " << PrintReg(Reg, RegInfo)
|
|
<< " to get a scratch register.\n");
|
|
SavedRegs.set(Reg);
|
|
ExtraCSSpill = true;
|
|
++Count;
|
|
}
|
|
|
|
// If we didn't find an extra callee-saved register to spill, create
|
|
// an emergency spill slot.
|
|
if (!ExtraCSSpill) {
|
|
const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
|
|
int FI = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), false);
|
|
RS->addScavengingFrameIndex(FI);
|
|
DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
|
|
<< " as the emergency spill slot.\n");
|
|
}
|
|
}
|
|
}
|