forked from OSchip/llvm-project
121 lines
4.4 KiB
LLVM
121 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
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; RUN: FileCheck --check-prefix=CHECK-LE %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \
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; RUN: FileCheck --check-prefix=CHECK-BE %s
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; Function Attrs: norecurse nounwind readnone
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define <4 x i32> @test_xxsplti32dx_1(<4 x i32> %a) {
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; CHECK-LE-LABEL: test_xxsplti32dx_1:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 0, 566
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 1, 566
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; CHECK-BE-NEXT: blr
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entry:
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%vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %vecins1
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}
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; Function Attrs: norecurse nounwind readnone
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define <4 x i32> @test_xxsplti32dx_2(<4 x i32> %a) {
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; CHECK-LE-LABEL: test_xxsplti32dx_2:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 1, 33
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 33
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; CHECK-BE-NEXT: blr
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entry:
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%vecins1 = shufflevector <4 x i32> <i32 33, i32 undef, i32 33, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %vecins1
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}
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; Function Attrs: norecurse nounwind readnone
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define <4 x i32> @test_xxsplti32dx_3(<4 x i32> %a) {
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; CHECK-LE-LABEL: test_xxsplti32dx_3:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 0, 12
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 1, 12
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; CHECK-BE-NEXT: blr
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entry:
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%vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 12, i32 undef, i32 12>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %vecins1
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}
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; Function Attrs: norecurse nounwind readnone
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define <4 x i32> @test_xxsplti32dx_4(<4 x i32> %a) {
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; CHECK-LE-LABEL: test_xxsplti32dx_4:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 1, -683
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 0, -683
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; CHECK-BE-NEXT: blr
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entry:
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%vecins1 = shufflevector <4 x i32> <i32 -683, i32 undef, i32 -683, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %vecins1
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}
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; Function Attrs: nounwind
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define <4 x float> @test_xxsplti32dx_5(<4 x float> %vfa) {
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; CHECK-LE-LABEL: test_xxsplti32dx_5:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 0, 1065353216
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 1, 1065353216
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; CHECK-BE-NEXT: blr
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entry:
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%vecins3.i = shufflevector <4 x float> %vfa, <4 x float> <float undef, float 1.000000e+00, float undef, float 1.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecins3.i
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}
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; Function Attrs: nounwind
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define <4 x float> @test_xxsplti32dx_6(<4 x float> %vfa) {
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; CHECK-LE-LABEL: test_xxsplti32dx_6:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 1, 1073741824
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 0, 1073741824
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; CHECK-BE-NEXT: blr
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entry:
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%vecins3.i = shufflevector <4 x float> <float 2.000000e+00, float undef, float 2.000000e+00, float undef>, <4 x float> %vfa, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecins3.i
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}
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; Function Attrs: norecurse nounwind readnone
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; Test to illustrate when the splat is narrower than 32-bits.
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define dso_local <4 x i32> @test_xxsplti32dx_7(<4 x i32> %a) local_unnamed_addr #0 {
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; CHECK-LE-LABEL: test_xxsplti32dx_7:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: xxsplti32dx vs34, 1, -1414812757
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_xxsplti32dx_7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsplti32dx vs34, 0, -1414812757
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; CHECK-BE-NEXT: blr
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entry:
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%vecins1 = shufflevector <4 x i32> <i32 -1414812757, i32 undef, i32 -1414812757, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %vecins1
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}
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