llvm-project/llvm/test/TableGen
Artem Belevich d75805e0e9 [tablegen] Fixed few !foreach evaluation issues.
* !foreach on lists didn't evaluate operands of the RHS operator.
  This made nested operators silently fail.
* A typo in the code could result in a wrong value substituted
  for an operation which produced a false '!foreach requires an operator' error.
* Keep recursion over the DAG within ForeachHelper. This simplifies
  things a bit as we no longer need to pass the Type around in order
  to prevent recursion.

Differential Revision: https://reviews.llvm.org/D43083

llvm-svn: 324758
2018-02-09 18:37:55 +00:00
..
2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AllowDuplicateRegisterNames.td [TableGen] Give the option of tolerating duplicate register names 2017-12-07 09:51:55 +00:00
AnonDefinitionOnDemand.td
AsmPredicateCondsEmission.td
AsmVariant.td [TableGen] Add a proper namespace to an Instruction in an AsmMatcher test. This is required after r307358. 2017-07-07 05:50:45 +00:00
BitOffsetDecoder.td
BitsInit.td
BitsInitOverflow.td
CStyleComment.td
ClassInstanceValue.td
ConcatenatedSubregs.td Address r311914 review comments 2017-08-28 20:11:27 +00:00
Dag.td
DefmInherit.td
DefmInsideMultiClass.td
DuplicateFieldValues.td [tablegen] Delete duplicates from a vector without skipping elements 2016-12-01 19:38:50 +00:00
FieldAccess.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
GlobalISelEmitter.td [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern 2018-01-29 21:09:12 +00:00
HwModeSelect.td TableGen support for parameterized register class information 2017-09-14 16:56:21 +00:00
Include.inc
Include.td
IntBitInit.td
LazyChange.td
LetInsideMultiClasses.td
ListArgs.td
ListArgsSimple.td
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
LoLoL.td
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
NestedForeach.td
Paste.td
RegisterBankEmitter.td TableGen: Fix infinite recursion in RegisterBankEmitter 2017-01-30 15:07:01 +00:00
RegisterEncoder.td [TableGen] Add EncoderMethod to RegisterOperand 2017-05-15 10:13:07 +00:00
RelTest.td [mips] Improve diagnostics for instruction mapping 2018-01-08 16:25:40 +00:00
SetTheory.td
SiblingForeach.td
Slice.td
String.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
TwoLevelName.td Add test cases that will show the bug that was fixed in r256725. 2016-01-13 07:53:11 +00:00
UnsetBitInit.td
UnterminatedComment.td Make shell redirection construct portable 2017-07-12 13:24:46 +00:00
ValidIdentifiers.td
cast-list-initializer.td TableGen: Support folding casts from bits to int 2015-07-31 01:12:06 +00:00
cast.td
defmclass.td
eq.td
eqbit.td
foreach-eval.td [tablegen] Fixed few !foreach evaluation issues. 2018-02-09 18:37:55 +00:00
foreach.td
if-empty-list-arg.td
if.td [TableGen] Make sure !if is evaluated throughout class inheritance. 2018-01-30 19:29:21 +00:00
ifbit.td
intrinsic-long-name.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
intrinsic-struct.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
intrinsic-varargs.td TableGen: Allow setting SDNodeProperties on intrinsics 2017-12-20 19:36:28 +00:00
lisp.td
list-element-bitref.td
listconcat.td
lit.local.cfg
math.td TableGen: Add operator !or 2016-11-15 06:49:28 +00:00
nested-comment.td
pr8330.td
strconcat.td
subst.td
subst2.td
trydecode-emission.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
trydecode-emission2.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
trydecode-emission3.td tests: accept different TargetOpcode values. 2016-07-07 17:51:42 +00:00
usevalname.td