forked from OSchip/llvm-project
117 lines
3.9 KiB
C++
117 lines
3.9 KiB
C++
//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Target/TargetInstrItineraries.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// TargetOperandInfo
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//===----------------------------------------------------------------------===//
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/// getRegClass - Get the register class for the operand, handling resolution
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/// of "symbolic" pointer register classes etc. If this is not a register
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/// operand, this returns null.
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const TargetRegisterClass *
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TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
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if (isLookupPtrRegClass())
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return TRI->getPointerRegClass(RegClass);
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// Instructions like INSERT_SUBREG do not have fixed register classes.
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if (RegClass < 0)
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return 0;
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// Otherwise just look it up normally.
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return TRI->getRegClass(RegClass);
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}
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//===----------------------------------------------------------------------===//
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// TargetInstrInfo
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//===----------------------------------------------------------------------===//
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TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
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unsigned numOpcodes)
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: Descriptors(Desc), NumOpcodes(numOpcodes) {
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}
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TargetInstrInfo::~TargetInstrInfo() {
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}
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unsigned
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TargetInstrInfo::getNumMicroOps(const MachineInstr *MI,
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const InstrItineraryData *ItinData) const {
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if (!ItinData || ItinData->isEmpty())
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return 1;
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unsigned Class = MI->getDesc().getSchedClass();
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unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
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if (UOps)
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return UOps;
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// The # of u-ops is dynamically determined. The specific target should
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// override this function to return the right number.
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return 1;
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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llvm_unreachable("Target didn't implement insertNoop!");
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}
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bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isTerminator()) return false;
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// Conditional branch is a special case.
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if (TID.isBranch() && !TID.isBarrier())
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return true;
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if (!TID.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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/// Measure the specified inline asm to determine an approximation of its
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/// length.
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/// Comments (which run till the next SeparatorChar or newline) do not
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/// count as an instruction.
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/// Any other non-whitespace text is considered an instruction, with
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/// multiple instructions separated by SeparatorChar or newlines.
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/// Variable-length instructions are not handled here; this function
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/// may be overloaded in the target code to do that.
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unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
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const MCAsmInfo &MAI) const {
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// Count the number of instructions in the asm.
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bool atInsnStart = true;
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unsigned Length = 0;
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for (; *Str; ++Str) {
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if (*Str == '\n' || *Str == MAI.getSeparatorChar())
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atInsnStart = true;
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if (atInsnStart && !isspace(*Str)) {
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Length += MAI.getMaxInstLength();
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atInsnStart = false;
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}
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if (atInsnStart && strncmp(Str, MAI.getCommentString(),
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strlen(MAI.getCommentString())) == 0)
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atInsnStart = false;
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}
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return Length;
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}
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