forked from OSchip/llvm-project
8233527b05
DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447 |
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| .. | ||
| README.txt | ||
| i32operations.c | ||
| i64operations.c | ||
| vecoperations.c | ||
README.txt
This directory contains code that's not part of the DejaGNU test suite, but is generally useful as various test harnesses. vecoperations.c: Various vector operation sanity checks, e.g., shuffles, 8-bit vector add and multiply.