forked from OSchip/llvm-project
c48aefb63b
A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999 |
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.. | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
ManagedStringPool.h | ||
NVPTX.h | ||
NVPTX.td | ||
NVPTXAllocaHoisting.cpp | ||
NVPTXAllocaHoisting.h | ||
NVPTXAsmPrinter.cpp | ||
NVPTXAsmPrinter.h | ||
NVPTXAssignValidGlobalNames.cpp | ||
NVPTXFrameLowering.cpp | ||
NVPTXFrameLowering.h | ||
NVPTXGenericToNVVM.cpp | ||
NVPTXISelDAGToDAG.cpp | ||
NVPTXISelDAGToDAG.h | ||
NVPTXISelLowering.cpp | ||
NVPTXISelLowering.h | ||
NVPTXImageOptimizer.cpp | ||
NVPTXInstrFormats.td | ||
NVPTXInstrInfo.cpp | ||
NVPTXInstrInfo.h | ||
NVPTXInstrInfo.td | ||
NVPTXIntrinsics.td | ||
NVPTXLowerAggrCopies.cpp | ||
NVPTXLowerAggrCopies.h | ||
NVPTXLowerAlloca.cpp | ||
NVPTXLowerArgs.cpp | ||
NVPTXMCExpr.cpp | ||
NVPTXMCExpr.h | ||
NVPTXMachineFunctionInfo.h | ||
NVPTXPeephole.cpp | ||
NVPTXPrologEpilogPass.cpp | ||
NVPTXRegisterInfo.cpp | ||
NVPTXRegisterInfo.h | ||
NVPTXRegisterInfo.td | ||
NVPTXReplaceImageHandles.cpp | ||
NVPTXSubtarget.cpp | ||
NVPTXSubtarget.h | ||
NVPTXTargetMachine.cpp | ||
NVPTXTargetMachine.h | ||
NVPTXTargetObjectFile.h | ||
NVPTXTargetTransformInfo.cpp | ||
NVPTXTargetTransformInfo.h | ||
NVPTXUtilities.cpp | ||
NVPTXUtilities.h | ||
NVVMIntrRange.cpp | ||
NVVMReflect.cpp | ||
cl_common_defines.h |