maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/mlir
History
Lei Zhang 93284120f2 [mlir][vector] Fix TransferOpReduceRank for 0-D tensors 
We cannot unconditionally generate memref.load ops for such cases;
need to check the source's type.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D114376
 		2021-11-22 12:30:46 -05:00
..
cmake/modules Re-apply "[mlir] Allow out-of-tree python building from installed MLIR." 2021-11-14 20:31:34 -08:00
docs [mlir] support recursive types in type conversion infra 2021-11-22 18:16:02 +01:00
examples [mlir] Move trait to InferTypeOpInterface 2021-11-21 14:41:12 -08:00
include [mlir] support recursive types in type conversion infra 2021-11-22 18:16:02 +01:00
lib [mlir][vector] Fix TransferOpReduceRank for 0-D tensors 2021-11-22 12:30:46 -05:00
python [mlir][Python] Fix generation of accessors for Optional 2021-11-18 09:42:57 +01:00
test [mlir][vector] Fix TransferOpReduceRank for 0-D tensors 2021-11-22 12:30:46 -05:00
tools [mlir] Fully qualify default generated type/attribute printer and parser 2021-11-18 20:24:00 +01:00
unittests [MLIR] PresburgerSetTest: fix comment and add a test case 2021-11-22 20:00:56 +05:30
utils [mlir][NFC] Replace references to Identifier with StringAttr 2021-11-16 17:36:26 +00:00
.clang-format
…
.clang-tidy NFC: .clang-tidy: Inherit configs from parents to improve maintainability 2021-06-08 08:25:59 -07:00
CMakeLists.txt [mlir] Add MLIR-C dylib. 2021-11-11 22:58:13 -08:00
LICENSE.TXT
…
README.md
…

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.