forked from OSchip/llvm-project
31 lines
862 B
LLVM
31 lines
862 B
LLVM
; RUN: llc -march=hexagon -enable-pipeliner < %s | FileCheck %s
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; A test that the Phi rewrite logic is correct.
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; CHECK: [[REG0:(r[0-9]+)]] = #0
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: memh([[REG0]]+#0) = #0
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define void @f0(i32 %a0) #0 {
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b0:
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%v0 = add i32 %a0, -4
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br label %b1
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b1: ; preds = %b1, %b0
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%v1 = phi i16* [ %v4, %b1 ], [ null, %b0 ]
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%v2 = phi i32 [ %v5, %b1 ], [ 0, %b0 ]
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%v3 = getelementptr inbounds i16, i16* %v1, i32 1
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store i16 0, i16* %v1, align 2
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%v4 = getelementptr inbounds i16, i16* %v1, i32 2
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store i16 0, i16* %v3, align 2
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%v5 = add nsw i32 %v2, 8
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%v6 = icmp slt i32 %v5, %v0
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br i1 %v6, label %b1, label %b2
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b2: ; preds = %b1
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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