forked from OSchip/llvm-project
67 lines
2.2 KiB
LLVM
67 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -enable-pipeliner -pipeliner-max-stages=2 < %s | FileCheck %s
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; Check that the pipelined code uses the proper address in the
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; prolog and the kernel. The bug occurs when the address computation
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; computes the same value twice.
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; CHECK: = addasl(r{{[0-9]+}},[[REG0:(r[0-9]+)]],#1)
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; CHECK-NOT: = addasl(r{{[0-9]+}},[[REG0]],#1)
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; Function Attrs: nounwind
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define void @f0(i32 %a0, i16* nocapture %a1) #0 {
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b0:
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br i1 undef, label %b2, label %b1
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b1: ; preds = %b0
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unreachable
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b2: ; preds = %b0
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br label %b3
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b3: ; preds = %b4, %b2
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br i1 undef, label %b4, label %b5
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b4: ; preds = %b3
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br label %b3
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b5: ; preds = %b3
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br i1 undef, label %b6, label %b7
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b6: ; preds = %b5
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unreachable
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b7: ; preds = %b5
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br i1 undef, label %b8, label %b12
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b8: ; preds = %b7
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br i1 undef, label %b9, label %b11
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b9: ; preds = %b9, %b8
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br i1 undef, label %b9, label %b10
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b10: ; preds = %b9
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br i1 undef, label %b12, label %b11
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b11: ; preds = %b11, %b10, %b8
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%v0 = phi i32 [ %v6, %b11 ], [ undef, %b8 ], [ undef, %b10 ]
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%v1 = phi i32 [ %v0, %b11 ], [ %a0, %b8 ], [ undef, %b10 ]
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%v2 = add nsw i32 %v1, -2
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%v3 = getelementptr inbounds i16, i16* %a1, i32 %v2
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%v4 = load i16, i16* %v3, align 2, !tbaa !0
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%v5 = getelementptr inbounds i16, i16* %a1, i32 %v0
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store i16 %v4, i16* %v5, align 2, !tbaa !0
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%v6 = add nsw i32 %v0, -1
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%v7 = icmp sgt i32 %v6, 0
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br i1 %v7, label %b11, label %b12
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b12: ; preds = %b11, %b10, %b7
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2}
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!2 = !{!"omnipotent char", !3}
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!3 = !{!"Simple C/C++ TBAA"}
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