llvm-project/llvm/test/CodeGen
Evandro Menezes c0571bd065 [AArch64] Improve macro fusion test case
Improve a vector in the test case for the fusion of address generation and
loads or stores.  Otherwise, NFC.

llvm-svn: 325839
2018-02-22 23:32:06 +00:00
..
AArch64 [AArch64] Improve macro fusion test case 2018-02-22 23:32:06 +00:00
AMDGPU AMDGPU: Do not combine loads/store across physreg defs 2018-02-21 13:31:35 +00:00
ARC
ARM Recommit: [ARM] f16 constant pool fix 2018-02-22 10:43:57 +00:00
AVR [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
BPF [BPF] Return true in enableMultipleCopyHints(). 2018-02-18 10:09:54 +00:00
Generic Made test dbg_value_fastisel.ll specific to AArch64 fast-isel. 2018-02-17 17:43:24 +00:00
Hexagon [Hexagon] Return true in enableMultipleCopyHints(). 2018-02-21 16:37:45 +00:00
Inputs
Lanai Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
MIR [GISel]: Verify COPIES involving generic registers. 2018-02-09 01:27:23 +00:00
MSP430 Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
Mips [mips] Generate memory dependencies for byVal arguments 2018-02-22 13:40:42 +00:00
NVPTX [DAGCombiner] Call ExtendUsesToFormExtLoad in (zext (and (load)))->(and (zextload)) even when the and does not have multiple uses 2018-02-15 20:20:32 +00:00
Nios2 [Nios2] Arithmetic instructions for R1 and R2 ISA. 2018-01-09 11:15:08 +00:00
PowerPC [PowerPC] Do not produce invalid CTR loop with an FRem 2018-02-22 03:02:41 +00:00
RISCV [RISCV] Revert r324172 now r323991 was reverted 2018-02-17 18:17:47 +00:00
SPARC [Sparc] Include __tls_get_addr in symbol table for TLS calls to it 2018-02-21 15:25:26 +00:00
SystemZ Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
Thumb [ARM] Fix issue with large xor constants. 2018-02-22 09:38:57 +00:00
Thumb2 [ARM] Return true in enableMultipleCopyHints(). 2018-02-16 09:51:01 +00:00
WebAssembly [WebAssembly] Add mechanisms for specifying an explicit import module name. 2018-02-09 23:13:22 +00:00
WinCFGuard Reland "Emit Function IDs table for Control Flow Guard" 2018-01-09 23:49:30 +00:00
WinEH
X86 [X86][AVX512] Add DQ+VLX scalar int<->fp tests cases for D43441 2018-02-22 16:29:08 +00:00
XCore Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00