forked from OSchip/llvm-project
e171a913d6
Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 llvm-svn: 307836 |
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| AArch64 | ||
| AMDGPU | ||
| ARM | ||
| AVR | ||
| AsmParser | ||
| COFF | ||
| Disassembler | ||
| ELF | ||
| Hexagon | ||
| Lanai | ||
| MachO | ||
| Markup | ||
| Mips | ||
| PowerPC | ||
| Sparc | ||
| SystemZ | ||
| WebAssembly | ||
| X86 | ||