maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Sanjay Patel bfee5a9b42 [x86] fix uses check in broadcast transform (PR38949) 
https://bugs.llvm.org/show_bug.cgi?id=38949

It's not clear to me that we even need a one-use check in this fold.
Ie, 2 independent loads might be better than a load+dependent shuffle.

Note that the existing re-use tests are not affected. We actually do form a
broadcast node in those tests now because there's no extra use of the 
insert_subvector node in those cases. But something later in isel pattern 
matching decides that it is not worth using a broadcast for the full load in 
those tests:

Legalized selection DAG: %bb.0 'test_broadcast_2f64_4f64_reuse:'
  t7: v2f64,ch = load<(load 16 from %ir.p0)> t0, t2, undef:i64
      t4: i64,ch = CopyFromReg t0, Register:i64 %1
    t10: ch = store<(store 16 into %ir.p1)> t7:1, t7, t4, undef:i64
      t18: v4f64 = insert_subvector undef:v4f64, t7, Constant:i64<0>
    t20: v4f64 = insert_subvector t18, t7, Constant:i64<2>

Becomes:
  t7: v2f64,ch = load<(load 16 from %ir.p0)> t0, t2, undef:i64
      t4: i64,ch = CopyFromReg t0, Register:i64 %1
    t10: ch = store<(store 16 into %ir.p1)> t7:1, t7, t4, undef:i64
    t21: v4f64 = X86ISD::SUBV_BROADCAST t7

ISEL: Starting selection on root node: t21: v4f64 = X86ISD::SUBV_BROADCAST t7
...
  Created node: t27: v4f64 = INSERT_SUBREG IMPLICIT_DEF:v4f64, t7, TargetConstant:i32<7>
  Morphed node: t21: v4f64 = VINSERTF128rr t27, t7, TargetConstant:i8<1>

llvm-svn: 342347
 		2018-09-16 15:41:56 +00:00
..
AArch64 [AArch64] Add integer abs testcases for D51873. 2018-09-13 17:11:25 +00:00
AMDGPU [AMDGPU] Ensure trig range reduction only used for subtargets that require it 2018-09-14 10:27:19 +00:00
ARC
…
ARM Revert r342210 "[ARM] bottom-top mul support in ARMParallelDSP" 2018-09-14 18:44:37 +00:00
AVR [AVR] Redefine the 'LSL' instruction as an alias of 'ADD' 2018-09-01 12:23:00 +00:00
BPF bpf: add missing RegState to notify MachineInstr verifier necessary register usage 2018-07-27 16:58:52 +00:00
Generic [MC/Dwarf] Unclamp DWARF linetables format on Darwin. 2018-09-13 13:13:50 +00:00
Hexagon [Hexagon] Use shuffles when lowering "gather" shufflevectors 2018-09-12 22:14:52 +00:00
Inputs
…
Lanai
…
MIR add IR flags to MI 2018-09-11 21:35:32 +00:00
MSP430 [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Mips [MIPS] Fix illegal type assert in single-float mode 2018-09-11 15:32:47 +00:00
NVPTX [NVPTX] Implement isLegalToVectorizeLoadChain 2018-08-27 17:29:43 +00:00
Nios2
…
PowerPC [PowerPC] Fix the calling convention for i1 arguments on PPC32 2018-09-14 21:26:05 +00:00
RISCV [RISCV] atomic_store_nn have a different layout to regular store 2018-08-27 07:08:18 +00:00
SPARC [Sparc] Use ANDN instead of AND if constant can be encoded more efficiently 2018-08-30 14:05:26 +00:00
SystemZ [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks) 2018-08-29 11:18:14 +00:00
Thumb CodeGen: Make computeRegisterLiveness search forward first 2018-08-30 07:18:10 +00:00
Thumb2 [SelectionDAG] Improve the legalisation lowering of UMULO. 2018-08-16 18:39:39 +00:00
WebAssembly [WebAssembly][NFC] Generalize operand numbers in SIMD tests 2018-09-15 01:12:48 +00:00
WinCFGuard Rename the cfguard module flag to cfguardtable 2018-08-10 09:48:53 +00:00
WinEH
…
X86 [x86] fix uses check in broadcast transform (PR38949) 2018-09-16 15:41:56 +00:00
XCore [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X) 2018-07-15 16:27:07 +00:00