forked from OSchip/llvm-project
41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
{
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"context" : "{ [] }",
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"name" : "%1 => %17",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "write",
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"relation" : "{ Stmt_4[i0, i1] -> MemRef_C[1536i0 + i1] }"
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}
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],
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"domain" : "{ Stmt_4[i0, i1] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 }",
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"name" : "Stmt_4",
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"schedule" : "{ Stmt_4[i0, i1] -> schedule[0, i0, 0, i1, 0, 0, 0] }"
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},
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_C[1536i0 + i1] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_A[1536i0 + i2] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_B[i1 + 1536i2] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_6[i0, i1, i2] -> MemRef_C[1536i0 + i1] }"
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}
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],
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"domain" : "{ Stmt_6[i0, i1, i2] : i0 >= 0 and i0 <= 1023 and i1 >= 0 and i1 <= 1023 and i2 >= 0 and i2 <= 1023 }",
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"name" : "Stmt_6",
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"schedule" : "{ Stmt_6[i0, i1, i2] -> schedule[1, i0, 0, i2, 0, i1, 0] }"
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}
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]
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}
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