forked from OSchip/llvm-project
30 lines
964 B
LLVM
30 lines
964 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=BASE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=slow-3ops-lea | FileCheck %s --check-prefix=SLOWLEA3
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; TODO: Should the 'cmpl' be 'dec' instead?
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; TODO: What if 'cmov' is 1 uop and full throughput (Ryzen)?
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define i32 @PR28968(i32 %x) {
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; BASE-LABEL: PR28968:
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; BASE: # %bb.0:
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; BASE-NEXT: xorl %eax, %eax
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; BASE-NEXT: cmpl $1, %edi
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; BASE-NEXT: sete %al
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; BASE-NEXT: leal -1(%rax,%rax), %eax
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; BASE-NEXT: retq
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;
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; SLOWLEA3-LABEL: PR28968:
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; SLOWLEA3: # %bb.0:
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; SLOWLEA3-NEXT: xorl %eax, %eax
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; SLOWLEA3-NEXT: cmpl $1, %edi
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; SLOWLEA3-NEXT: sete %al
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; SLOWLEA3-NEXT: leal (%rax,%rax), %eax
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; SLOWLEA3-NEXT: addl $-1, %eax
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; SLOWLEA3-NEXT: retq
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%cmp = icmp eq i32 %x, 1
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%sel = select i1 %cmp, i32 1, i32 -1
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ret i32 %sel
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}
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