forked from OSchip/llvm-project
439 lines
15 KiB
LLVM
439 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2
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; fold (srem x, 1) -> 0
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define i32 @combine_srem_by_one(i32 %x) {
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; CHECK-LABEL: combine_srem_by_one:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, 1
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ret i32 %1
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}
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define <4 x i32> @combine_vec_srem_by_one(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_one:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_one:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %1
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}
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; fold (srem x, -1) -> 0
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define i32 @combine_srem_by_negone(i32 %x) {
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; CHECK-LABEL: combine_srem_by_negone:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, -1
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ret i32 %1
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}
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define <4 x i32> @combine_vec_srem_by_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_negone:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_negone:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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; TODO fold (srem x, INT_MIN)
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define i32 @combine_srem_by_minsigned(i32 %x) {
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; CHECK-LABEL: combine_srem_by_minsigned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: sarl $31, %eax
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; CHECK-NEXT: shrl %eax
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; CHECK-NEXT: addl %edi, %eax
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; CHECK-NEXT: andl $-2147483648, %eax # imm = 0x80000000
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; CHECK-NEXT: subl %eax, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, -2147483648
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ret i32 %1
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}
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define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_minsigned:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $1, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_minsigned:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_minsigned:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX2-NEXT: vpsrld $1, %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
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ret <4 x i32> %1
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}
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; TODO fold (srem x, x) -> 0
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define i32 @combine_srem_dupe(i32 %x) {
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; CHECK-LABEL: combine_srem_dupe:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %edi
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: retq
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%1 = srem i32 %x, %x
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ret i32 %1
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}
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define <4 x i32> @combine_vec_srem_dupe(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_dupe:
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; SSE: # %bb.0:
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; SSE-NEXT: pextrd $1, %xmm0, %ecx
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; SSE-NEXT: movl %ecx, %eax
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; SSE-NEXT: cltd
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; SSE-NEXT: idivl %ecx
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; SSE-NEXT: movl %edx, %ecx
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; SSE-NEXT: movd %xmm0, %esi
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; SSE-NEXT: movl %esi, %eax
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; SSE-NEXT: cltd
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; SSE-NEXT: idivl %esi
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; SSE-NEXT: movd %edx, %xmm1
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; SSE-NEXT: pinsrd $1, %ecx, %xmm1
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; SSE-NEXT: pextrd $2, %xmm0, %ecx
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; SSE-NEXT: movl %ecx, %eax
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; SSE-NEXT: cltd
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; SSE-NEXT: idivl %ecx
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; SSE-NEXT: pinsrd $2, %edx, %xmm1
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; SSE-NEXT: pextrd $3, %xmm0, %ecx
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; SSE-NEXT: movl %ecx, %eax
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; SSE-NEXT: cltd
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; SSE-NEXT: idivl %ecx
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; SSE-NEXT: pinsrd $3, %edx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_dupe:
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; AVX: # %bb.0:
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; AVX-NEXT: vpextrd $1, %xmm0, %ecx
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; AVX-NEXT: movl %ecx, %eax
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; AVX-NEXT: cltd
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; AVX-NEXT: idivl %ecx
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; AVX-NEXT: movl %edx, %ecx
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; AVX-NEXT: vmovd %xmm0, %esi
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; AVX-NEXT: movl %esi, %eax
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; AVX-NEXT: cltd
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; AVX-NEXT: idivl %esi
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; AVX-NEXT: vmovd %edx, %xmm1
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %ecx
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; AVX-NEXT: movl %ecx, %eax
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; AVX-NEXT: cltd
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; AVX-NEXT: idivl %ecx
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; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %ecx
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; AVX-NEXT: movl %ecx, %eax
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; AVX-NEXT: cltd
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; AVX-NEXT: idivl %ecx
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; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, %x
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ret <4 x i32> %1
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}
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; fold (srem x, y) -> (urem x, y) iff x and y are positive
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define <4 x i32> @combine_vec_srem_by_pos0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pos0:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_pos0:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_pos0:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [3,3,3,3]
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
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%2 = srem <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_srem_by_pos1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pos1:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{.*}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_pos1:
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; AVX: # %bb.0:
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; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
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%2 = srem <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %2
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}
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; fold (srem x, (1 << c)) -> x - (x / (1 << c)) * (1 << c).
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define <4 x i32> @combine_vec_srem_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2a:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $30, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE-NEXT: psubd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_pow2a:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_pow2a:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX2-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967292,4294967292,4294967292,4294967292]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2a_neg(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2a_neg:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $30, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: psrad $2, %xmm1
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pxor %xmm3, %xmm3
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; SSE-NEXT: psubd %xmm1, %xmm3
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; SSE-NEXT: pslld $2, %xmm3
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; SSE-NEXT: psubd %xmm3, %xmm2
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_srem_by_pow2a_neg:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX-NEXT: vpsrad $2, %xmm1, %xmm1
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpslld $2, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -4, i32 -4, i32 -4, i32 -4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2b:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $31, %xmm1
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrad $31, %xmm2
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; SSE-NEXT: movdqa %xmm2, %xmm3
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; SSE-NEXT: psrld $29, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1,2,3],xmm3[4,5,6,7]
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; SSE-NEXT: psrld $30, %xmm2
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psrad $2, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm1[0,1,2,3],xmm3[4,5,6,7]
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; SSE-NEXT: psrad $3, %xmm1
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; SSE-NEXT: psrad $1, %xmm2
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; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1],xmm3[2,3,4,5,6,7]
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm3
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; SSE-NEXT: psubd %xmm3, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_pow2b:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrld $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2
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; AVX1-NEXT: vpsrld $29, %xmm2, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpsrld $30, %xmm2, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $3, %xmm1, %xmm2
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; AVX1-NEXT: vpsrad $1, %xmm1, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpsrad $2, %xmm1, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
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; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_pow2b:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3]
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; AVX2-NEXT: vpsravd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
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; AVX2-NEXT: vpsllvd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 1, i32 2, i32 4, i32 8>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_srem_by_pow2b_neg(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_srem_by_pow2b_neg:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrld $28, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psrld $30, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: movdqa %xmm0, %xmm2
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; SSE-NEXT: psrld $31, %xmm2
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; SSE-NEXT: psrld $29, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrad $4, %xmm2
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; SSE-NEXT: movdqa %xmm1, %xmm3
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; SSE-NEXT: psrad $2, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psrad $3, %xmm2
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; SSE-NEXT: psrad $1, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: psubd %xmm1, %xmm2
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; SSE-NEXT: pmulld {{.*}}(%rip), %xmm2
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; SSE-NEXT: psubd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: combine_vec_srem_by_pow2b_neg:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $28, %xmm1, %xmm2
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; AVX1-NEXT: vpsrld $30, %xmm1, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpsrld $31, %xmm0, %xmm3
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; AVX1-NEXT: vpsrld $29, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm3[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $4, %xmm1, %xmm2
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; AVX1-NEXT: vpsrad $2, %xmm1, %xmm3
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; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
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; AVX1-NEXT: vpsrad $3, %xmm1, %xmm3
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; AVX1-NEXT: vpsrad $1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm3[4,5,6,7]
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
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; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_srem_by_pow2b_neg:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1
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; AVX2-NEXT: vpsravd {{.*}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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%1 = srem <4 x i32> %x, <i32 -2, i32 -4, i32 -8, i32 -16>
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ret <4 x i32> %1
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}
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; OSS-Fuzz #6883
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; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883
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define i32 @ossfuzz6883() {
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; CHECK-LABEL: ossfuzz6883:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rax), %ecx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %ecx
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; CHECK-NEXT: movl %edx, %esi
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; CHECK-NEXT: movl $1, %edi
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; CHECK-NEXT: cltd
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; CHECK-NEXT: idivl %edi
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; CHECK-NEXT: movl %edx, %edi
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: divl %edi
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; CHECK-NEXT: andl %esi, %eax
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; CHECK-NEXT: retq
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%B17 = or i32 0, 2147483647
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%L6 = load i32, i32* undef
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%B11 = sdiv i32 %L6, %L6
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%B13 = udiv i32 %B17, %B17
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%B14 = srem i32 %B11, %B13
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%B16 = srem i32 %L6, %L6
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%B10 = udiv i32 %L6, %B14
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%B6 = and i32 %B16, %B10
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ret i32 %B6
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}
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