forked from OSchip/llvm-project
254 lines
9.4 KiB
LLVM
254 lines
9.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CHECK,XOP
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512
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; fold (rot (rot x, c1), c2) -> rot x, c1+c2
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define <4 x i32> @combine_vec_rot_rot(<4 x i32> %x) {
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; SSE2-LABEL: combine_vec_rot_rot:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [524288,131072,32768,8192]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm2, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: combine_vec_rot_rot:
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; XOP: # %bb.0:
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; XOP-NEXT: vprotd {{.*}}(%rip), %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_rot_rot:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
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; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_rot:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vprolvd {{.*}}(%rip), %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
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%2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 12, i32 13, i32 14, i32 15>
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%5 = shl <4 x i32> %3, <i32 20, i32 19, i32 18, i32 17>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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define <4 x i32> @combine_vec_rot_rot_splat(<4 x i32> %x) {
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; SSE2-LABEL: combine_vec_rot_rot_splat:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa %xmm0, %xmm1
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; SSE2-NEXT: psrld $25, %xmm1
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; SSE2-NEXT: pslld $7, %xmm0
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: combine_vec_rot_rot_splat:
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; XOP: # %bb.0:
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; XOP-NEXT: vprotd $7, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_rot_rot_splat:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrld $25, %xmm0, %xmm1
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; AVX2-NEXT: vpslld $7, %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_rot_splat:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vprold $7, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>
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%2 = shl <4 x i32> %x, <i32 29, i32 29, i32 29, i32 29>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>
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%5 = shl <4 x i32> %3, <i32 10, i32 10, i32 10, i32 10>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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define <4 x i32> @combine_vec_rot_rot_splat_zero(<4 x i32> %x) {
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; CHECK-LABEL: combine_vec_rot_rot_splat_zero:
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; CHECK: # %bb.0:
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; CHECK-NEXT: retq
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%1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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%2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%3 = or <4 x i32> %1, %2
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%4 = lshr <4 x i32> %3, <i32 31, i32 31, i32 31, i32 31>
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%5 = shl <4 x i32> %3, <i32 1, i32 1, i32 1, i32 1>
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%6 = or <4 x i32> %4, %5
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ret <4 x i32> %6
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}
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define <4 x i32> @rotate_demanded_bits(<4 x i32>, <4 x i32>) {
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; SSE2-LABEL: rotate_demanded_bits:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE2-NEXT: pslld $23, %xmm1
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm2, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: rotate_demanded_bits:
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; XOP: # %bb.0:
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; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: rotate_demanded_bits:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [30,30,30,30]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: rotate_demanded_bits:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%3 = and <4 x i32> %1, <i32 30, i32 30, i32 30, i32 30>
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%4 = shl <4 x i32> %0, %3
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%5 = sub nsw <4 x i32> zeroinitializer, %3
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%6 = and <4 x i32> %5, <i32 30, i32 30, i32 30, i32 30>
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%7 = lshr <4 x i32> %0, %6
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%8 = or <4 x i32> %7, %4
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ret <4 x i32> %8
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}
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define <4 x i32> @rotate_demanded_bits_2(<4 x i32>, <4 x i32>) {
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; SSE2-LABEL: rotate_demanded_bits_2:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE2-NEXT: pslld $23, %xmm1
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm2, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: rotate_demanded_bits_2:
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; XOP: # %bb.0:
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; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: rotate_demanded_bits_2:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [23,23,23,23]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: rotate_demanded_bits_2:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%3 = and <4 x i32> %1, <i32 23, i32 23, i32 23, i32 23>
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%4 = shl <4 x i32> %0, %3
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%5 = sub nsw <4 x i32> zeroinitializer, %3
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%6 = and <4 x i32> %5, <i32 31, i32 31, i32 31, i32 31>
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%7 = lshr <4 x i32> %0, %6
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%8 = or <4 x i32> %7, %4
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ret <4 x i32> %8
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}
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define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
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; SSE2-LABEL: rotate_demanded_bits_3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: paddd %xmm1, %xmm1
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; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
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; SSE2-NEXT: pslld $23, %xmm1
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
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; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm2, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: rotate_demanded_bits_3:
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; XOP: # %bb.0:
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; XOP-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: rotate_demanded_bits_3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [30,30,30,30]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: rotate_demanded_bits_3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%3 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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%4 = and <4 x i32> %3, <i32 30, i32 30, i32 30, i32 30>
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%5 = shl <4 x i32> %0, %4
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%6 = sub <4 x i32> zeroinitializer, %3
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%7 = and <4 x i32> %6, <i32 30, i32 30, i32 30, i32 30>
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%8 = lshr <4 x i32> %0, %7
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%9 = or <4 x i32> %5, %8
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ret <4 x i32> %9
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}
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