forked from OSchip/llvm-project
116 lines
4.0 KiB
C++
116 lines
4.0 KiB
C++
//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-emitter"
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#include "ARM.h"
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#include "ARMInstrInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class ARMMCCodeEmitter : public MCCodeEmitter {
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ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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MCContext &Ctx;
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public:
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ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
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: TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
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assert(0 && "ARMMCCodeEmitter::ARMMCCodeEmitter() not yet implemented.");
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}
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~ARMMCCodeEmitter() {}
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unsigned getNumFixupKinds() const {
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assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
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return 0;
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}
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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static MCFixupKindInfo rtn;
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assert(0 && "ARMMCCodeEmitter::getFixupKindInfo() not yet implemented.");
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return rtn;
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}
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static unsigned GetARMRegNum(const MCOperand &MO) {
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// FIXME: getARMRegisterNumbering() is sufficient?
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assert(0 && "ARMMCCodeEmitter::GetARMRegNum() not yet implemented.");
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return 0;
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}
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void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
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OS << (char)C;
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++CurByte;
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}
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void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
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raw_ostream &OS) const {
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// Output the constant in little endian byte order.
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for (unsigned i = 0; i != Size; ++i) {
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EmitByte(Val & 255, CurByte, OS);
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Val >>= 8;
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}
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}
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void EmitImmediate(const MCOperand &Disp,
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unsigned ImmSize, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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int ImmOffset = 0) const;
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void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
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const MCInst &MI, const TargetInstrDesc &Desc,
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raw_ostream &OS) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &,
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TargetMachine &TM,
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MCContext &Ctx) {
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return new ARMMCCodeEmitter(TM, Ctx);
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}
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void ARMMCCodeEmitter::
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EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
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assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
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}
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/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
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///
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/// MemOperand is the operand # of the start of a memory operand if present. If
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/// Not present, it is -1.
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void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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int MemOperand, const MCInst &MI,
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const TargetInstrDesc &Desc,
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raw_ostream &OS) const {
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assert(0 && "ARMMCCodeEmitter::EmitOpcodePrefix() not yet implemented.");
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}
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void ARMMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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assert(0 && "ARMMCCodeEmitter::EncodeInstruction() not yet implemented.");
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}
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