| .. |
|
AArch64
|
[AArch64] define isExtractSubvectorCheap
|
2018-03-06 16:54:55 +00:00 |
|
AMDGPU
|
[AMDGPU] Fix lowering OpenCL enqueue_kernel
|
2018-03-06 16:04:39 +00:00 |
|
ARC
|
…
|
|
|
ARM
|
[ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB
|
2018-03-02 13:02:55 +00:00 |
|
AVR
|
[AVR] Remove the earlyclobber flag from LDDWRdYQ
|
2018-03-06 11:20:25 +00:00 |
|
BPF
|
bpf: New codegen testcases for 32-bit subregister support
|
2018-02-23 23:49:33 +00:00 |
|
Generic
|
Revert "[DWARFv5] Emit file 0 to the line table."
|
2018-03-06 03:15:21 +00:00 |
|
Hexagon
|
[Hexagon] Update more testcases
|
2018-03-06 19:15:58 +00:00 |
|
Inputs
|
…
|
|
|
Lanai
|
Followup on Proposal to move MIR physical register namespace to '$' sigil.
|
2018-01-31 22:04:26 +00:00 |
|
MIR
|
[MIRParser] Accept overloaded intrinsic names w/o type suffixes
|
2018-02-28 23:51:49 +00:00 |
|
MSP430
|
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
|
2018-01-19 17:13:12 +00:00 |
|
Mips
|
[TLS] use emulated TLS if the target supports only this mode
|
2018-02-28 17:48:55 +00:00 |
|
NVPTX
|
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
|
2018-03-01 22:32:25 +00:00 |
|
Nios2
|
[Nios2] Arithmetic instructions for R1 and R2 ISA.
|
2018-01-09 11:15:08 +00:00 |
|
PowerPC
|
[PowerPC] Do not emit record-form rotates when record-form andi suffices
|
2018-03-05 19:27:16 +00:00 |
|
RISCV
|
[RISCV] Update two tests after r326208
|
2018-02-28 08:20:47 +00:00 |
|
SPARC
|
Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"
|
2018-02-27 16:59:10 +00:00 |
|
SystemZ
|
[SystemZ] Fix test cases after r326613
|
2018-03-02 21:22:42 +00:00 |
|
Thumb
|
[ARM] Fix access to stack arguments when re-aligning SP in Armv6m
|
2018-03-02 15:47:14 +00:00 |
|
Thumb2
|
ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR.
|
2018-02-27 19:00:59 +00:00 |
|
WebAssembly
|
[WebAssembly] Add mechanisms for specifying an explicit import module name.
|
2018-02-09 23:13:22 +00:00 |
|
WinCFGuard
|
Reland "Emit Function IDs table for Control Flow Guard"
|
2018-01-09 23:49:30 +00:00 |
|
WinEH
|
…
|
|
|
X86
|
[X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
|
2018-03-06 18:56:33 +00:00 |
|
XCore
|
[XCore] Return true in enableMultipleCopyHints().
|
2018-02-26 08:03:32 +00:00 |
18484de34b