forked from OSchip/llvm-project
84 lines
3.9 KiB
LLVM
84 lines
3.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}s_cvt_pk_u16_u32:
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SX:[0-9]+]]:[[SY:[0-9]+]]{{\]}}, s[0:1], 0x{{b|2c}}
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; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
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; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, s[[SX]], [[VY]]
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; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, s[[SX]], [[VY]]
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define amdgpu_kernel void @s_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %y)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_cvt_pk_u16_samereg_i32:
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; GCN: s_load_dword [[X:s[0-9]+]]
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; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
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define amdgpu_kernel void @s_cvt_pk_u16_samereg_i32(i32 addrspace(1)* %out, i32 %x) #0 {
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%result = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %x, i32 %x)
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%r = bitcast <2 x i16> %result to i32
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_u16_u32:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GCN: {{buffer|flat|global}}_load_dword [[B:v[0-9]+]]
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; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, [[A]], [[B]]
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; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, [[A]], [[B]]
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define amdgpu_kernel void @v_cvt_pk_u16_u32(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%b = load volatile i32, i32 addrspace(1)* %b.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 %b)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_reg_imm:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; GCN: v_cvt_pk_u16_u32{{(_e64)*}} v{{[0-9]+}}, [[A]], 1
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define amdgpu_kernel void @v_cvt_pk_u16_u32_reg_imm(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 %a, i32 1)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_cvt_pk_u16_u32_imm_reg:
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; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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; SI: v_cvt_pk_u16_u32_e32 v{{[0-9]+}}, 1, [[A]]
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; VI: v_cvt_pk_u16_u32 v{{[0-9]+}}, 1, [[A]]
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define amdgpu_kernel void @v_cvt_pk_u16_u32_imm_reg(i32 addrspace(1)* %out, i32 addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
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%a = load volatile i32, i32 addrspace(1)* %a.gep
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%cvt = call <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32 1, i32 %a)
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%r = bitcast <2 x i16> %cvt to i32
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store i32 %r, i32 addrspace(1)* %out.gep
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ret void
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}
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declare <2 x i16> @llvm.amdgcn.cvt.pk.u16(i32, i32) #1
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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