forked from OSchip/llvm-project
203 lines
8.0 KiB
LLVM
203 lines
8.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s
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; EG-LABEL: {{^}}test_fmin_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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define amdgpu_kernel void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) #0 {
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%val = call float @llvm.minnum.f32(float %a, float %b)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}test_fmin_v2f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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define amdgpu_kernel void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
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%val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
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store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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; EG-LABEL: {{^}}test_fmin_v4f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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; EG: MIN_DX10 {{.*}}[[OUT]]
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define amdgpu_kernel void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 {
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%val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
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store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; EG-LABEL: {{^}}test_fmin_v8f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
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define amdgpu_kernel void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 {
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%val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b)
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store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
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ret void
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}
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; EG-LABEL: {{^}}test_fmin_v16f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]]
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]]
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W
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; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W
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; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X
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; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y
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; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z
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; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W
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define amdgpu_kernel void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 {
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%val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b)
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store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 1.0, float 2.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_nan_nan:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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; EG: 2143289344({{nan|1\.#QNAN0e\+00}})
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define amdgpu_kernel void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_val_nan:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_nan_val:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_p0_p0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 0.0, float 0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_p0_n0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float 0.0, float -0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_n0_p0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float -0.0, float 0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}constant_fold_fmin_f32_n0_n0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG-NOT: MIN_DX10
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; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}}
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define amdgpu_kernel void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.minnum.f32(float -0.0, float -0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}fmin_var_immediate_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define amdgpu_kernel void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) #0 {
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%val = call float @llvm.minnum.f32(float %a, float 2.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}fmin_immediate_var_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define amdgpu_kernel void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) #0 {
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%val = call float @llvm.minnum.f32(float 2.0, float %a)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}fmin_var_literal_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define amdgpu_kernel void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) #0 {
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%val = call float @llvm.minnum.f32(float %a, float 99.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; EG-LABEL: {{^}}fmin_literal_var_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]]
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; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}}
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define amdgpu_kernel void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) #0 {
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%val = call float @llvm.minnum.f32(float 99.0, float %a)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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declare float @llvm.minnum.f32(float, float) #1
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declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #1
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declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
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declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #1
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declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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