forked from OSchip/llvm-project
762 lines
25 KiB
C++
762 lines
25 KiB
C++
//===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Copies from VGPR to SGPR registers are illegal and the register coalescer
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/// will sometimes generate these illegal copies in situations like this:
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///
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/// Register Class <vsrc> is the union of <vgpr> and <sgpr>
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///
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/// BB0:
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/// %0 <sgpr> = SCALAR_INST
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/// %1 <vsrc> = COPY %0 <sgpr>
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %2 <vgpr> = VECTOR_INST
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/// %3 <vsrc> = COPY %2 <vgpr>
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/// BB2:
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/// %4 <vsrc> = PHI %1 <vsrc>, <%bb.0>, %3 <vrsc>, <%bb.1>
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/// %5 <vgpr> = VECTOR_INST %4 <vsrc>
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///
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///
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/// The coalescer will begin at BB0 and eliminate its copy, then the resulting
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/// code will look like this:
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///
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/// BB0:
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/// %0 <sgpr> = SCALAR_INST
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %2 <vgpr> = VECTOR_INST
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/// %3 <vsrc> = COPY %2 <vgpr>
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/// BB2:
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/// %4 <sgpr> = PHI %0 <sgpr>, <%bb.0>, %3 <vsrc>, <%bb.1>
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/// %5 <vgpr> = VECTOR_INST %4 <sgpr>
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///
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/// Now that the result of the PHI instruction is an SGPR, the register
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/// allocator is now forced to constrain the register class of %3 to
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/// <sgpr> so we end up with final code like this:
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///
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/// BB0:
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/// %0 <sgpr> = SCALAR_INST
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/// ...
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/// BRANCH %cond BB1, BB2
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/// BB1:
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/// %2 <vgpr> = VECTOR_INST
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/// %3 <sgpr> = COPY %2 <vgpr>
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/// BB2:
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/// %4 <sgpr> = PHI %0 <sgpr>, <%bb.0>, %3 <sgpr>, <%bb.1>
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/// %5 <vgpr> = VECTOR_INST %4 <sgpr>
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///
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/// Now this code contains an illegal copy from a VGPR to an SGPR.
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///
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/// In order to avoid this problem, this pass searches for PHI instructions
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/// which define a <vsrc> register and constrains its definition class to
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/// <vgpr> if the user of the PHI's definition register is a vector instruction.
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/// If the PHI's definition class is constrained to <vgpr> then the coalescer
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/// will be unable to perform the COPY removal from the above example which
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/// ultimately led to the creation of an illegal COPY.
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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#include <list>
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#include <map>
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#include <tuple>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "si-fix-sgpr-copies"
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static cl::opt<bool> EnableM0Merge(
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"amdgpu-enable-merge-m0",
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cl::desc("Merge and hoist M0 initializations"),
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cl::init(false));
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namespace {
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class SIFixSGPRCopies : public MachineFunctionPass {
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MachineDominatorTree *MDT;
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MachinePostDominatorTree *MPDT;
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DenseMap<MachineBasicBlock *, SetVector<MachineBasicBlock*>> PDF;
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void computePDF(MachineFunction * MF);
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void printPDF();
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#endif
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public:
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static char ID;
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SIFixSGPRCopies() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "SI Fix SGPR copies"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachinePostDominatorTree>();
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AU.addPreserved<MachinePostDominatorTree>();
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(SIFixSGPRCopies, DEBUG_TYPE,
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"SI Fix SGPR copies", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(SIFixSGPRCopies, DEBUG_TYPE,
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"SI Fix SGPR copies", false, false)
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char SIFixSGPRCopies::ID = 0;
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char &llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID;
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FunctionPass *llvm::createSIFixSGPRCopiesPass() {
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return new SIFixSGPRCopies();
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}
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static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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if (!MI.getOperand(i).isReg() ||
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!TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
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continue;
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if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
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return true;
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}
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return false;
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}
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static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
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getCopyRegClasses(const MachineInstr &Copy,
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const SIRegisterInfo &TRI,
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const MachineRegisterInfo &MRI) {
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unsigned DstReg = Copy.getOperand(0).getReg();
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unsigned SrcReg = Copy.getOperand(1).getReg();
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const TargetRegisterClass *SrcRC =
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TargetRegisterInfo::isVirtualRegister(SrcReg) ?
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MRI.getRegClass(SrcReg) :
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TRI.getPhysRegClass(SrcReg);
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// We don't really care about the subregister here.
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// SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
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const TargetRegisterClass *DstRC =
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TargetRegisterInfo::isVirtualRegister(DstReg) ?
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MRI.getRegClass(DstReg) :
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TRI.getPhysRegClass(DstReg);
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return std::make_pair(SrcRC, DstRC);
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}
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static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
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const TargetRegisterClass *DstRC,
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const SIRegisterInfo &TRI) {
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return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
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}
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static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
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const TargetRegisterClass *DstRC,
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const SIRegisterInfo &TRI) {
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return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
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}
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static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI,
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const SIRegisterInfo *TRI,
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const SIInstrInfo *TII) {
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MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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auto &Src = MI.getOperand(1);
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned SrcReg = Src.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
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!TargetRegisterInfo::isVirtualRegister(DstReg))
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return false;
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for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
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const auto *UseMI = MO.getParent();
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if (UseMI == &MI)
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continue;
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if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
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UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
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!TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
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return false;
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}
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// Change VGPR to SGPR destination.
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MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg)));
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return true;
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}
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// Distribute an SGPR->VGPR copy of a REG_SEQUENCE into a VGPR REG_SEQUENCE.
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//
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// SGPRx = ...
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// SGPRy = REG_SEQUENCE SGPRx, sub0 ...
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// VGPRz = COPY SGPRy
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//
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// ==>
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//
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// VGPRx = COPY SGPRx
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// VGPRz = REG_SEQUENCE VGPRx, sub0
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//
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// This exposes immediate folding opportunities when materializing 64-bit
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// immediates.
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static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI,
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const SIRegisterInfo *TRI,
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const SIInstrInfo *TII,
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MachineRegisterInfo &MRI) {
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assert(MI.isRegSequence());
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unsigned DstReg = MI.getOperand(0).getReg();
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if (!TRI->isSGPRClass(MRI.getRegClass(DstReg)))
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return false;
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if (!MRI.hasOneUse(DstReg))
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return false;
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MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg);
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if (!CopyUse.isCopy())
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return false;
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// It is illegal to have vreg inputs to a physreg defining reg_sequence.
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if (TargetRegisterInfo::isPhysicalRegister(CopyUse.getOperand(0).getReg()))
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return false;
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const TargetRegisterClass *SrcRC, *DstRC;
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std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
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if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
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return false;
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if (tryChangeVGPRtoSGPRinCopy(CopyUse, TRI, TII))
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return true;
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// TODO: Could have multiple extracts?
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unsigned SubReg = CopyUse.getOperand(1).getSubReg();
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if (SubReg != AMDGPU::NoSubRegister)
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return false;
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MRI.setRegClass(DstReg, DstRC);
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// SGPRx = ...
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// SGPRy = REG_SEQUENCE SGPRx, sub0 ...
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// VGPRz = COPY SGPRy
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// =>
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// VGPRx = COPY SGPRx
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// VGPRz = REG_SEQUENCE VGPRx, sub0
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MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
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for (unsigned I = 1, N = MI.getNumOperands(); I != N; I += 2) {
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unsigned SrcReg = MI.getOperand(I).getReg();
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unsigned SrcSubReg = MI.getOperand(I).getSubReg();
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const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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assert(TRI->isSGPRClass(SrcRC) &&
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"Expected SGPR REG_SEQUENCE to only have SGPR inputs");
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SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg);
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const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC);
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unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC);
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BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
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TmpReg)
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.add(MI.getOperand(I));
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MI.getOperand(I).setReg(TmpReg);
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}
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CopyUse.eraseFromParent();
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return true;
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}
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static bool phiHasVGPROperands(const MachineInstr &PHI,
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const MachineRegisterInfo &MRI,
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const SIRegisterInfo *TRI,
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const SIInstrInfo *TII) {
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for (unsigned i = 1; i < PHI.getNumOperands(); i += 2) {
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unsigned Reg = PHI.getOperand(i).getReg();
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if (TRI->hasVGPRs(MRI.getRegClass(Reg)))
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return true;
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}
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return false;
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}
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static bool phiHasBreakDef(const MachineInstr &PHI,
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const MachineRegisterInfo &MRI,
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SmallSet<unsigned, 8> &Visited) {
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for (unsigned i = 1; i < PHI.getNumOperands(); i += 2) {
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unsigned Reg = PHI.getOperand(i).getReg();
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if (Visited.count(Reg))
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continue;
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Visited.insert(Reg);
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MachineInstr *DefInstr = MRI.getVRegDef(Reg);
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switch (DefInstr->getOpcode()) {
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default:
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break;
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case AMDGPU::SI_BREAK:
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case AMDGPU::SI_IF_BREAK:
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case AMDGPU::SI_ELSE_BREAK:
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return true;
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case AMDGPU::PHI:
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if (phiHasBreakDef(*DefInstr, MRI, Visited))
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return true;
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}
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}
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return false;
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}
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static bool hasTerminatorThatModifiesExec(const MachineBasicBlock &MBB,
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const TargetRegisterInfo &TRI) {
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for (MachineBasicBlock::const_iterator I = MBB.getFirstTerminator(),
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E = MBB.end(); I != E; ++I) {
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if (I->modifiesRegister(AMDGPU::EXEC, &TRI))
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return true;
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}
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return false;
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}
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static bool isSafeToFoldImmIntoCopy(const MachineInstr *Copy,
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const MachineInstr *MoveImm,
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const SIInstrInfo *TII,
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unsigned &SMovOp,
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int64_t &Imm) {
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if (Copy->getOpcode() != AMDGPU::COPY)
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return false;
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if (!MoveImm->isMoveImmediate())
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return false;
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const MachineOperand *ImmOp =
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TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0);
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if (!ImmOp->isImm())
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return false;
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// FIXME: Handle copies with sub-regs.
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if (Copy->getOperand(0).getSubReg())
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return false;
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switch (MoveImm->getOpcode()) {
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default:
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return false;
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case AMDGPU::V_MOV_B32_e32:
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SMovOp = AMDGPU::S_MOV_B32;
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break;
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case AMDGPU::V_MOV_B64_PSEUDO:
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SMovOp = AMDGPU::S_MOV_B64;
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break;
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}
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Imm = ImmOp->getImm();
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return true;
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}
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template <class UnaryPredicate>
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bool searchPredecessors(const MachineBasicBlock *MBB,
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const MachineBasicBlock *CutOff,
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UnaryPredicate Predicate) {
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if (MBB == CutOff)
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return false;
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DenseSet<const MachineBasicBlock *> Visited;
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SmallVector<MachineBasicBlock *, 4> Worklist(MBB->pred_begin(),
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MBB->pred_end());
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while (!Worklist.empty()) {
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MachineBasicBlock *MBB = Worklist.pop_back_val();
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if (!Visited.insert(MBB).second)
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continue;
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if (MBB == CutOff)
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continue;
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if (Predicate(MBB))
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return true;
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Worklist.append(MBB->pred_begin(), MBB->pred_end());
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}
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return false;
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}
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// Checks if there is potential path From instruction To instruction.
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// If CutOff is specified and it sits in between of that path we ignore
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// a higher portion of the path and report it is not reachable.
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static bool isReachable(const MachineInstr *From,
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const MachineInstr *To,
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const MachineBasicBlock *CutOff,
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MachineDominatorTree &MDT) {
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// If either From block dominates To block or instructions are in the same
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// block and From is higher.
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if (MDT.dominates(From, To))
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return true;
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const MachineBasicBlock *MBBFrom = From->getParent();
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const MachineBasicBlock *MBBTo = To->getParent();
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if (MBBFrom == MBBTo)
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return false;
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// Instructions are in different blocks, do predecessor search.
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// We should almost never get here since we do not usually produce M0 stores
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// other than -1.
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return searchPredecessors(MBBTo, CutOff, [MBBFrom]
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(const MachineBasicBlock *MBB) { return MBB == MBBFrom; });
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}
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// Hoist and merge identical SGPR initializations into a common predecessor.
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// This is intended to combine M0 initializations, but can work with any
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// SGPR. A VGPR cannot be processed since we cannot guarantee vector
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// executioon.
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static bool hoistAndMergeSGPRInits(unsigned Reg,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT) {
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// List of inits by immediate value.
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using InitListMap = std::map<unsigned, std::list<MachineInstr *>>;
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InitListMap Inits;
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// List of clobbering instructions.
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SmallVector<MachineInstr*, 8> Clobbers;
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bool Changed = false;
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for (auto &MI : MRI.def_instructions(Reg)) {
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MachineOperand *Imm = nullptr;
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for (auto &MO: MI.operands()) {
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if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
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(!MO.isImm() && !MO.isReg()) || (MO.isImm() && Imm)) {
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Imm = nullptr;
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break;
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} else if (MO.isImm())
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Imm = &MO;
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}
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if (Imm)
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Inits[Imm->getImm()].push_front(&MI);
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else
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Clobbers.push_back(&MI);
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}
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for (auto &Init : Inits) {
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auto &Defs = Init.second;
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for (auto I1 = Defs.begin(), E = Defs.end(); I1 != E; ) {
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MachineInstr *MI1 = *I1;
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for (auto I2 = std::next(I1); I2 != E; ) {
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MachineInstr *MI2 = *I2;
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// Check any possible interference
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auto intereferes = [&](MachineBasicBlock::iterator From,
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MachineBasicBlock::iterator To) -> bool {
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assert(MDT.dominates(&*To, &*From));
|
|
|
|
auto interferes = [&MDT, From, To](MachineInstr* &Clobber) -> bool {
|
|
const MachineBasicBlock *MBBFrom = From->getParent();
|
|
const MachineBasicBlock *MBBTo = To->getParent();
|
|
bool MayClobberFrom = isReachable(Clobber, &*From, MBBTo, MDT);
|
|
bool MayClobberTo = isReachable(Clobber, &*To, MBBTo, MDT);
|
|
if (!MayClobberFrom && !MayClobberTo)
|
|
return false;
|
|
if ((MayClobberFrom && !MayClobberTo) ||
|
|
(!MayClobberFrom && MayClobberTo))
|
|
return true;
|
|
// Both can clobber, this is not an interference only if both are
|
|
// dominated by Clobber and belong to the same block or if Clobber
|
|
// properly dominates To, given that To >> From, so it dominates
|
|
// both and located in a common dominator.
|
|
return !((MBBFrom == MBBTo &&
|
|
MDT.dominates(Clobber, &*From) &&
|
|
MDT.dominates(Clobber, &*To)) ||
|
|
MDT.properlyDominates(Clobber->getParent(), MBBTo));
|
|
};
|
|
|
|
return (llvm::any_of(Clobbers, interferes)) ||
|
|
(llvm::any_of(Inits, [&](InitListMap::value_type &C) {
|
|
return C.first != Init.first &&
|
|
llvm::any_of(C.second, interferes);
|
|
}));
|
|
};
|
|
|
|
if (MDT.dominates(MI1, MI2)) {
|
|
if (!intereferes(MI2, MI1)) {
|
|
DEBUG(dbgs() << "Erasing from "
|
|
<< printMBBReference(*MI2->getParent()) << " "
|
|
<< *MI2);
|
|
MI2->eraseFromParent();
|
|
Defs.erase(I2++);
|
|
Changed = true;
|
|
continue;
|
|
}
|
|
} else if (MDT.dominates(MI2, MI1)) {
|
|
if (!intereferes(MI1, MI2)) {
|
|
DEBUG(dbgs() << "Erasing from "
|
|
<< printMBBReference(*MI1->getParent()) << " "
|
|
<< *MI1);
|
|
MI1->eraseFromParent();
|
|
Defs.erase(I1++);
|
|
Changed = true;
|
|
break;
|
|
}
|
|
} else {
|
|
auto *MBB = MDT.findNearestCommonDominator(MI1->getParent(),
|
|
MI2->getParent());
|
|
if (!MBB) {
|
|
++I2;
|
|
continue;
|
|
}
|
|
|
|
MachineBasicBlock::iterator I = MBB->getFirstNonPHI();
|
|
if (!intereferes(MI1, I) && !intereferes(MI2, I)) {
|
|
DEBUG(dbgs() << "Erasing from "
|
|
<< printMBBReference(*MI1->getParent()) << " " << *MI1
|
|
<< "and moving from "
|
|
<< printMBBReference(*MI2->getParent()) << " to "
|
|
<< printMBBReference(*I->getParent()) << " " << *MI2);
|
|
I->getParent()->splice(I, MI2->getParent(), MI2);
|
|
MI1->eraseFromParent();
|
|
Defs.erase(I1++);
|
|
Changed = true;
|
|
break;
|
|
}
|
|
}
|
|
++I2;
|
|
}
|
|
++I1;
|
|
}
|
|
}
|
|
|
|
if (Changed)
|
|
MRI.clearKillFlags(Reg);
|
|
|
|
return Changed;
|
|
}
|
|
|
|
void SIFixSGPRCopies::computePDF(MachineFunction *MF) {
|
|
MachineFunction::iterator B = MF->begin();
|
|
MachineFunction::iterator E = MF->end();
|
|
for (; B != E; ++B) {
|
|
if (B->succ_size() > 1) {
|
|
for (auto S : B->successors()) {
|
|
MachineDomTreeNode *runner = MPDT->getNode(&*S);
|
|
MachineDomTreeNode *sentinel = MPDT->getNode(&*B)->getIDom();
|
|
while (runner && runner != sentinel) {
|
|
PDF[runner->getBlock()].insert(&*B);
|
|
runner = runner->getIDom();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
void SIFixSGPRCopies::printPDF() {
|
|
dbgs() << "\n######## PostDominanceFrontiers set #########\n";
|
|
for (auto &I : PDF) {
|
|
dbgs() << "PDF[ " << I.first->getNumber() << "] : ";
|
|
for (auto &J : I.second) {
|
|
dbgs() << J->getNumber() << ' ';
|
|
}
|
|
dbgs() << '\n';
|
|
}
|
|
dbgs() << "\n##############################################\n";
|
|
}
|
|
#endif
|
|
|
|
bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
|
|
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
const SIRegisterInfo *TRI = ST.getRegisterInfo();
|
|
const SIInstrInfo *TII = ST.getInstrInfo();
|
|
MDT = &getAnalysis<MachineDominatorTree>();
|
|
MPDT = &getAnalysis<MachinePostDominatorTree>();
|
|
PDF.clear();
|
|
computePDF(&MF);
|
|
DEBUG(printPDF());
|
|
|
|
SmallVector<MachineInstr *, 16> Worklist;
|
|
|
|
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
|
|
BI != BE; ++BI) {
|
|
MachineBasicBlock &MBB = *BI;
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
|
|
I != E; ++I) {
|
|
MachineInstr &MI = *I;
|
|
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
continue;
|
|
case AMDGPU::COPY:
|
|
case AMDGPU::WQM:
|
|
case AMDGPU::WWM: {
|
|
// If the destination register is a physical register there isn't really
|
|
// much we can do to fix this.
|
|
if (!TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg()))
|
|
continue;
|
|
|
|
const TargetRegisterClass *SrcRC, *DstRC;
|
|
std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
|
|
if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
|
|
unsigned SrcReg = MI.getOperand(1).getReg();
|
|
if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
|
|
TII->moveToVALU(MI);
|
|
break;
|
|
}
|
|
|
|
MachineInstr *DefMI = MRI.getVRegDef(SrcReg);
|
|
unsigned SMovOp;
|
|
int64_t Imm;
|
|
// If we are just copying an immediate, we can replace the copy with
|
|
// s_mov_b32.
|
|
if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) {
|
|
MI.getOperand(1).ChangeToImmediate(Imm);
|
|
MI.addImplicitDefUseOperands(MF);
|
|
MI.setDesc(TII->get(SMovOp));
|
|
break;
|
|
}
|
|
TII->moveToVALU(MI);
|
|
} else if (isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) {
|
|
tryChangeVGPRtoSGPRinCopy(MI, TRI, TII);
|
|
}
|
|
|
|
break;
|
|
}
|
|
case AMDGPU::PHI: {
|
|
unsigned Reg = MI.getOperand(0).getReg();
|
|
if (!TRI->isSGPRClass(MRI.getRegClass(Reg)))
|
|
break;
|
|
|
|
// We don't need to fix the PHI if all the source blocks
|
|
// have no divergent control dependecies
|
|
bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII);
|
|
if (!HasVGPROperand) {
|
|
bool Uniform = true;
|
|
MachineBasicBlock * Join = MI.getParent();
|
|
for (auto &O : MI.explicit_operands()) {
|
|
if (O.isMBB()) {
|
|
MachineBasicBlock * Source = O.getMBB();
|
|
SetVector<MachineBasicBlock*> &SourcePDF = PDF[Source];
|
|
SetVector<MachineBasicBlock*> &JoinPDF = PDF[Join];
|
|
SetVector<MachineBasicBlock*> CDList;
|
|
for (auto &I : SourcePDF) {
|
|
if (!JoinPDF.count(I) || /* back edge */MDT->dominates(Join, I)) {
|
|
if (hasTerminatorThatModifiesExec(*I, *TRI))
|
|
Uniform = false;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (Uniform) {
|
|
DEBUG(dbgs() << "Not fixing PHI for uniform branch: " << MI << '\n');
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If a PHI node defines an SGPR and any of its operands are VGPRs,
|
|
// then we need to move it to the VALU.
|
|
//
|
|
// Also, if a PHI node defines an SGPR and has all SGPR operands
|
|
// we must move it to the VALU, because the SGPR operands will
|
|
// all end up being assigned the same register, which means
|
|
// there is a potential for a conflict if different threads take
|
|
// different control flow paths.
|
|
//
|
|
// For Example:
|
|
//
|
|
// sgpr0 = def;
|
|
// ...
|
|
// sgpr1 = def;
|
|
// ...
|
|
// sgpr2 = PHI sgpr0, sgpr1
|
|
// use sgpr2;
|
|
//
|
|
// Will Become:
|
|
//
|
|
// sgpr2 = def;
|
|
// ...
|
|
// sgpr2 = def;
|
|
// ...
|
|
// use sgpr2
|
|
//
|
|
// The one exception to this rule is when one of the operands
|
|
// is defined by a SI_BREAK, SI_IF_BREAK, or SI_ELSE_BREAK
|
|
// instruction. In this case, there we know the program will
|
|
// never enter the second block (the loop) without entering
|
|
// the first block (where the condition is computed), so there
|
|
// is no chance for values to be over-written.
|
|
|
|
SmallSet<unsigned, 8> Visited;
|
|
if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) {
|
|
DEBUG(dbgs() << "Fixing PHI: " << MI);
|
|
TII->moveToVALU(MI);
|
|
}
|
|
break;
|
|
}
|
|
case AMDGPU::REG_SEQUENCE:
|
|
if (TRI->hasVGPRs(TII->getOpRegClass(MI, 0)) ||
|
|
!hasVGPROperands(MI, TRI)) {
|
|
foldVGPRCopyIntoRegSequence(MI, TRI, TII, MRI);
|
|
continue;
|
|
}
|
|
|
|
DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
|
|
|
|
TII->moveToVALU(MI);
|
|
break;
|
|
case AMDGPU::INSERT_SUBREG: {
|
|
const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
|
|
DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
|
|
Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
|
|
Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
|
|
if (TRI->isSGPRClass(DstRC) &&
|
|
(TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
|
|
DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
|
|
TII->moveToVALU(MI);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (MF.getTarget().getOptLevel() > CodeGenOpt::None && EnableM0Merge)
|
|
hoistAndMergeSGPRInits(AMDGPU::M0, MRI, *MDT);
|
|
|
|
return true;
|
|
}
|