forked from OSchip/llvm-project
41 lines
1.3 KiB
YAML
41 lines
1.3 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
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...
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# GCN-LABEL: name: fold_imm_non_ssa{{$}}
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# GCN: %0:vgpr_32 = V_MOV_B32_e32 123, implicit %exec
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# GCN: %2:vgpr_32 = V_ADD_I32_e32 456, %0, implicit-def %vcc, implicit %exec
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name: fold_imm_non_ssa
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_64 }
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body: |
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bb.0:
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%0 = COPY undef %0
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%0 = V_MOV_B32_e32 123, implicit %exec
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%1 = V_MOV_B32_e32 456, implicit %exec
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%2, %vcc = V_ADD_I32_e64 %0, %1, implicit %exec
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S_ENDPGM
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...
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# GCN-LABEL: name: fold_partially_defined_superreg{{$}}
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# GCN: %1:vgpr_32 = V_MOV_B32_e32 456, implicit %exec
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# GCN: %2:vgpr_32 = V_ADD_I32_e32 123, %1, implicit-def %vcc, implicit %exec
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name: fold_partially_defined_superreg
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: vreg_64 }
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body: |
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bb.0:
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undef %3.sub0 = V_MOV_B32_e32 123, implicit %exec, implicit-def %3
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%1 = V_MOV_B32_e32 456, implicit %exec
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%2, %vcc = V_ADD_I32_e64 %3.sub0, %1, implicit %exec
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S_ENDPGM
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...
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